Item 1. Business
ITEM 1. BUSINESS
General
QuickLogic Corporation was founded in 1988 and reincorporated in Delaware in 1999. We provide innovative, programmable silicon and software platforms to enable our customers to develop custom hardware products in a fast time-to-market and cost-effective way. Specifically, we are a fabless semiconductor company with a variety of products: embedded FPGA ("eFPGA") intellectual property ("IP"), low power, multi-core semiconductor system-on-chips ("SoCs"), discrete FPGAs, and AI software. Our customers can use our eFPGA IP for hardware acceleration and pre-processing in their Application Specific Integrated Circuit (ASIC) products, our SoCs to run our customers' software and build their hardware around, and our discrete FPGAs to implement their custom functionality. The Analytics Toolkit from SensiML Corporation ("SensiML"), our wholly-owned subsidiary, provides an end-to-end Artificial Intelligence / Machine Learning solution with accurate sensor algorithms using AI technology. The full range of platforms, software tools, and eFPGA IP enables the practical and efficient adoption of AI, voice, and sensor processing across Aerospace, and Defense, Consumer/Industrial IoT, and Consumer Electronics markets.
Our new products include the following: eFPGA IP Licensing business, associated professional services, consisting of development and integration of eFPGA technology into custom semiconductor solutions, our silicon products consisting of EOS™, QuickAI™, ArcticLink® III, PolarPro®3, PolarPro II, PolarPro, and Eclipse II products. In addition to delivering our own semiconductor solutions, our new products category includes our AI/ML Software Platform from our wholly-owned subsidiary company, SensiML, which includes Software as a Service (SaaS) subscriptions for development, per unit license fees when deployed in production, and proof-of-concept services, all of which are also included in the new products revenue category. Our mature products include primarily FPGA families named PASIC®3 and QuickRAM®, as well as programming hardware and design software.
For our IP and silicon platforms, we collaborate with multiple partners on co-marketing and/or co-selling initiatives. These partners could have primary business lines in semiconductor IP, Design Services, semiconductor foundry, semiconductor assembly and test, and others.
For our AI/ML Software, SensiML collaborates with several microcontroller and sensor manufacturers to integrate the microcontroller and/or sensor manufacturers’ development kits with SensiML’s Analytics Toolkit in order to showcase combined solutions for AI/ML applications. Currently, these collaborations include Infineon Technologies, On Semiconductor Corp., Microchip Technology Inc., Silicon Laboratories, Inc., STMicroelectronics N.V., Arduino, NXP Semiconductors N.V., Raspberry Pi, and Nordic Semiconductor.
Our eFPGA IP is currently developed on 12nm, 16nm, 22nm, 28nm, 40nm, 65nm, 90nm, 130nm, and 250nm process nodes with a roadmap to more advanced nodes. The licensable IP is generated by our automated compiler tool called Australis™, which enables our engineers to create an eFPGA IP for our licensees that they can then integrate into their SoC without significant involvement by QuickLogic. We believe this flow enables a scalable development and support model for QuickLogic. For our eFPGA strategy, we typically work with semiconductor manufacturing partners prior to this IP being licensed to a SoC company.
We have changed our manufacturing strategies to reduce the cost of our silicon solution platforms to enable their use in a range of unique products ranging from low to high volume. Our EOS S3, EOS S3AI, QuickAI and ArcticLink III silicon platforms combine mixed signal physical functions and hard-wired logic alongside our field programmable logic. Our EOS S3, EOS S3AI, and ArcticLink III solution platforms are manufactured on process nodes where we can benefit from smaller die sizes and lower power consumption. We typically implement sophisticated logic blocks and mixed signal functions in hard-wired logic because it is very cost-effective and energy efficient. We use small form factor packages, which are less expensive to manufacture and include smaller pin counts. Reduced pin counts result in lower costs for our customers' printed circuit board space and routing. Furthermore, our SRAM reprogrammable silicon platforms can be programmed in-system by our customers, and therefore, we do not incur programming costs, lowering the overall cost of ownership to our customers. We expect to continue to invest in silicon solution platforms and manufacturing technologies that make us competitive for the variety of markets and applications that programmable logic serves.
In order to grow our revenue from its current level, we depend upon increased revenue from our new products, including existing new product platforms and platforms currently in development. We expect our business growth to be driven mainly by eFPGA IP and our silicon solutions, with additional contributions from SensiML AI Software. Therefore, our revenue growth needs to be strong enough to enable us to sustain profitability while we continue to invest in the development, sale, and marketing of our new solution platforms, IP, and software.
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Available Information
Our corporate headquarters are located at 2220 Lundy Avenue, San Jose, California 95131. We can be reached at (408) 990-4000, and our website address is www.quicklogic.com . The information on our website is not incorporated herein by reference and is not a part of this Form 10-K. Our common stock trades on the Nasdaq Capital Market under the symbol “QUIK.” Our annual reports on Form 10-K, quarterly reports on Form 10-Q, current reports on Form 8-K, and amendments to such reports are available, free of charge, on our website home page as soon as reasonably practicable after we electronically file such materials with, or furnish them to, the Securities and Exchange Commission, or the SEC. Copies of the materials filed by the Company with the SEC are also available on the SEC’s website at www.sec.gov . A copy of our Code of Conduct and Ethics is posted on our website at https://ir.quicklogic.com/governance-docs. Any changes to or waiver from this Code of Conduct and Ethics will be posted to this page on our website.
Fiscal Year
Our fiscal year ends on the Sunday closest to December 31. References to Fiscal Years 2023, 2022, and 2021 refer to the Fiscal Years ended December 31, 2023 , January 1, 2023 , and January 2, 2022 , respectively.
Industry Background
Historically, system processing capability was built using a homogenous architecture, meaning one that consisted of the use of only one type of technology. This could be one or more instances of a single processor type, or only programmable logic. More recently, there is a general trend in the semiconductor market that enhanced processing capability can come from the adoption of more heterogeneous architectures. Examples of this trend are the inclusion of one or more general purpose processor cores (e.g., Arm or RISC-V) in conjunction with programmable logic. This type of architecture enables the end user to partition their application workloads across the heterogeneous cores so that the most appropriate core is used for a given workload, often concurrently. Generally, this is viewed as the most optimal way to design systems that need to optimize for performance or battery life. The heterogeneity can be implemented as multiple discrete devices on a Printed Circuit Board (PCB), multiple IP cores in a monolithic device, or as multiple devices (e.g., chiplets) integrated into an advanced package.
An important underlying trend for the Aerospace and Defense, and Industrial markets is that there is a need for a high degree of fragmentation of system functionality. This drives a need for a time and cost-efficient product development flow while maintaining the ability to extend the life cycle of a given design through design changes and uniquely optimize designs for new workloads and/or algorithms that need to be deployed (e.g., deploying more advanced AI algorithms in the future). Development time and non-recurring engineering ("NRE") costs tend to be more of the focus for hardware products in these markets rather than the bill of materials cost.
We believe these industry trends are shifting the demand among different classes of core silicon. The following are the four main classes of non-memory core silicon:
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Microcontrollers ("MCUs") are typically small, low-power hardware products on a single integrated circuit that contain a processor core, memory, and a number of peripherals. They are designed to be programmed with software for embedded applications;
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Application Specific Standard Products ("ASSPs") other than processors, are fixed-function hardware products designed to address a relatively narrow set of applications. These hardware products typically integrate a number of common peripherals or functions, and the functionality of these hardware products is fixed prior to wafer fabrication;
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Programmable Logic Devices ("PLDs") are general-purpose hardware products, which can be used by a variety of electronic systems manufacturers and are customized after purchase for a specific application. FPGAs are a subset of PLDs and are typically used to implement complex system functions; and
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Application Specific Integrated Circuits ("ASICs") are custom hardware products designed and fabricated to meet the needs of one specific application for one end-customer. Structured ASICs, a sub-category of ASICs, provide a limited amount of custom content to broaden the applicability of a device for additional applications.
ASSPs are offered broadly to the market, making it challenging for a system designer to create differentiated products from these hardware products alone. In many situations, the available ASSPs may not directly implement the desired function and the system designer is required to use a combination of ASSPs to achieve the desired result at the expense of increased cost, product size, and power consumption. As standards evolve or new standards are developed, ASSPs may not be available to implement desired functions.
System designers can customize their products using programmable logic, ASICs or MCUs. The competitive dynamic between these classes of core silicon is well understood. High development risks, development costs, and opportunity costs are incurred when using ASICs to produce custom hardware products with either very low unit production cost or unique functionality that is only achievable with a customer ASIC solution. Suppliers of programmable logic hardware products, which have lower development and market risks and development costs relative to ASICs, have aggressively reduced the unit cost of their products over time, making programmable logic hardware products the solution of choice for custom products unless the volume is very high or the functionality and/or operating environment is unique. These cost reduction efforts have significantly increased the volume required to justify the total cost of an ASIC.
Field Programmable Gate Array ("FPGA") technology has been used historically by system companies and OEMs to develop and deploy customer-specific functionality with fast time-to-market and low development costs. End market use includes Aerospace and Defense, Industrial, Computing, Communications, IoT, and Consumer. According to a recent research report published by Grand View Research, the FPGA market is expected to grow at >10% Compound Annual Growth Rate ("CAGR") from 2023 to 2030. Of that, the Aerospace and Defense segment is expected to expand at the fastest CAGR of 12.7% over the same forecast period. The emergence of embedded field programmable gate array IP technology ("eFPGA IP") has particularly favored the aerospace and defense industry by offering even better integration, reliability, and low power options over the use of traditional discrete FPGAs.
The Aerospace and Defense, and Industrial markets are well served by existing core silicon or custom ASIC development. Although much of these market's uses are generally not as price, power, and size sensitive, there are use cases for reducing size, weight and power. When there is a strong need for a custom solution to address specific functionality or operating environment (e.g., high radiation, extended temperature ranges, etc.), designers often turn to discrete FPGAs, or in some cases when standard FPGAs do not exist, an ASIC. QuickLogic FPGAs have a loyal following in certain segments of these markets, particularly when instant-on, energy efficiency, high reliability, or intellectual property security is important.
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In the past two years, QuickLogic has also entered into multiple, large eFPGA-related contracts with customers in the Aerospace and Defense market and expects to continue to do so in the future. Historically, the Defense market has followed QuickLogic’s mature products revenue trend, but recent advancements in QuickLogic’s Australis IP generator tool, the recent Strategic Radiation Hardened FPGA contract for the U.S. Department of Defense, participation in the DARPA Toolbox, and other eFPGA-related contracts with the Defense Industrial Base have enabled renewed interest from customers in this area. Consequently, QuickLogic expects these trends to be a primary growth driver.
Markets and Product Technology
We market our programmable logic (FPGAs and eFPGA IP) solutions primarily to Defense Industrial Base contractors, U.S. Government entities, and System OEMs, and fabless semiconductor companies. These customers may value one or more of our product categories. A solution can be based on our programmable technology, which enables customized designs, low power, flexibility, rapid time-to-market, longer time-in-market, and lower total cost of ownership. We are capable of providing complete solutions because of our investment in developing the low power IP and software required to implement specific functions, along with sensor software algorithms optimized for our architecture. In some cases, we develop the IPs and either software or firmware ourselves and, in other cases, we utilize third parties to develop the mixed signal physical layers, logic, and/or software.
We market our SoC and SensiML solutions to OEMs and ODMs offering differentiated Consumer/IoT products, to processor vendors wishing to expand their served available market, and to sensor manufacturers and sensor processing software companies wishing to expand their ecosystems. Our target markets for our SoC and SensiML products include Consumer/Industrial IoT and Consumer Electronics.
By using our silicon platforms, our IPs, our software, and our in-depth architecture knowledge, we can deliver energy efficient custom solutions that blend the benefits of traditional ASSPs with the flexibility, product proliferation, differentiation, and low total cost of ownership advantages of programmable logic.
Our product technology consists of five major elements:
1. Programmable Logic Technology
Our programmable logic enables our customers to customize their hardware platforms. We have two distinct types of programmable logic – Reprogrammable and One-Time Programmable ("OTP"). Within our Reprogrammable logic architecture, we can utilize standard foundry processes (e.g., CMOS-logic process with foundry-provided SRAM memory elements) or more unique processes (e.g., foundry-provided CMOS logic processes and third-party-provided memory elements (e.g., MRAM)). We can choose the appropriate process technology based on our customers’ requirements. Our SRAM-reprogrammable logic is the basis of our eFPGA IP License initiative and is the logic used in our EOS S3, EOS S3 LV, and EOS S3AI products. An example of the unique process combination is when we use foundry-provided CMOS with MRAM in the Strategic Radiation Hardened FPGA program for which we are the prime contractor.
The second type of is our programmable logic is our ViaLink® OTP technology. ViaLink is our proprietary and patented technology and possesses the characteristics of non-volatility and instant-on, very low standby power, low dynamic power, small form factor, power cycles easily and quickly are required.
2. Semiconductor Intellectual Property
We develop semiconductor intellectual property (IP) cores for licensing to our customers or for use within our own devices. Licensable eFPGA IP based on our Field Programmable Gate Array technology is called “embedded FPGA IP”. The eFPGA IP is generated by our automated IP compiler tool called Australis™, which enables our engineers to create an eFPGA IP for our licensees that they can then integrate into their SoC without significant involvement by us. We believe this flow enables a scalable development and support model for our company. Additionally, we may develop and provide other IP blocks that our customers can use in conjunction with our eFPGA IP, such as signal processing / digital filter functions, hardware acceleration, processor offloading, and various bus interface functions.
3. FPGA User Tools
We develop, maintain and support software tools that our customers use to program their designs into our FPGA, eFPGA IP and SoC products. By design, all programmable logic technology is unconfigured in its default state after manufacturing. Designers using programmable logic must configure the state of the programmable logic to match their requirements; this is accomplished by a suite of tools commonly referred to as FPGA User Tools. There are two such categories of FPGA User Tools – proprietary and open-source. Historically, FPGA/eFPGA vendors have provided only proprietary versions of these tools to their customers. For our Mature products, we continue to support a 100% proprietary FPGA User Tool. For our new products and eFPGA IP, we support a 100% open-source version, as well as a hybrid FPGA User Tool called Aurora that combines open-source and proprietary technology.
4. Silicon Platforms
We have two types of silicon platforms, discrete FPGAs and SoCs that embed FPGA technology. We have a variety of discrete FPGAs – historically based on our ViaLink technology, more recently based on our Reprogrammable technology (either SRAM- or MRAM-based configuration). We also have multiple silicon platforms that fall under the SoC category - ArcticLink and EOS S3, EOS S3 LV, and EOS S3AI. Our SoC platforms combine mixed signal physical functions, hard-wired logic, and programmable logic on one device. Adding hard-wired IP enables us to deliver more logic at lower cost and lower power while the programmable logic allows us to provide solutions that can be rapidly customized to differentiate products, add features, and reduce system development costs. This combination of mixed signal, hard-wired logic, and programmable logic enables us to deliver low cost, small form factor solutions that can be customized for a particular customer or market requirements while lowering the total cost of ownership.
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5. Artificial Intelligence / Machine Learning (AI/ML) Software
Through our wholly-owned subsidiary company, SensiML, we develop and optimize an end-to-end software suite that provides developers with a practical means for developing IoT sensor algorithms using AI. Each component of the software suite handles specific steps to progress from initial raw sensor data collection using prototype hardware to optimized firmware code generation, validation and testing, and post-ship algorithm updates and continuous learning enhancements. SensiML Data Studio (formerly the Data Capture Lab) is a full-featured client tool that enables rapid, efficient, and collaborative multi-user data collection, cleansing, labeling, and metadata annotation of custom application datasets. SensiML Analytics Studio is a cloud service component that uses labeled datasets to deliver device-optimized firmware for a chosen endpoint product. SensiML Test App is used to quickly and efficiently validate final device firmware and test for the proper behavior, accuracy, and performance of the algorithm empirically on actual endpoint hardware. Lastly, the SensiML Application Programmer’s Interface ("API") is a simplified interface to extend the SensiML algorithms and manage advanced features like edge model tuning and continuous learning updates to the cloud.
Marketing, Sales and Customers
We monetize our technology through hardware product sales and eFPGA IP licenses, with any necessary corresponding work delivered via professional engineering services, SensiML Analytics Toolkit subscriptions, and per unit royalties. We specialize in enhancing the user experience in leading edge IoT hardware products. For our customers, we enable hardware and sensor algorithmic differentiation quickly, cost-effectively, and at low power. For our partners, we expand their reach into new segments and new use cases, thereby expanding the served available market for their existing hardware products.
Our embedded FPGA technology gives ASIC and SoC developers the benefit of flexibility to make design changes post-manufacturing changes at very fast time-to- and time-in-market, while keeping power consumption low. Our multi-core sensor processing products such as ArcticLink 3 S1, ArcticLink 3 S2, EOS 3, EOS S3 LV, and EOS S3AI provide an extremely power-efficient approach for real-time multi-modal (vision, motion, voice, location, biometric, and environmental) sensor processing independently of the cloud. Our SensiML Analytics Toolkit is cutting-edge software that enables ultra-low power IoT endpoints that implement AI to transform raw sensor data into meaningful insight at the device itself. The toolkit also provides an end-to-end development platform spanning data collection, labeling, algorithm and firmware auto generation, and testing.
We recognize that our markets require a range of solutions, and we intend to work with market-leading companies to combine silicon solution platforms, packaging technology, FPGA User Tools, sensor software algorithms, software drivers and firmware, to meet the product proliferation, high bandwidth, time-to-market, time-in-market, and form factor requirements of our customers. We intend to continue to define and implement compelling solutions for our target customers and partners.
We believe our solutions are resonating with our target customers who value lower power consumption, platform design flexibility, rapid time-to-market, longer time-in-market, and low total cost of ownership available through the use of our solutions.
We sell our products through a network of sales managers in North America, Europe, and Asia. In addition to our corporate headquarters in San Jose, California, we have international sales operations in Japan and the United Kingdom. Our sales personnel and independent sales representatives are responsible for sales and application support for a given region, focusing on major strategic accounts, and managing our channel sales partners such as distributors.
Customers typically order our products through our distributor s. Currently, we have eight active distributors in North America and a network of seventeen active distributors and sales representatives throughout Eu rope and Asia to support our international business. eFPGA IP customers and SensiML SaaS subscribers typically enter into licensing agreements directly with QuickLogic and SensiML, respectively.
We also have an Aerospace and Defense, industrial, and IoT product customer base that purchases our mature silicon products. We expect to continue to offer silicon hardware products to these customers, as well as new eFPGA IP for when these customers choose to implement their own silicon platform solution.
One customer represented approximately 70% of our total revenue for the year ended December 31, 2023 . Three customers represented 20%, 16%, and 12% of our total revenue f or the year ended January 1, 2023 . In addition, a noteworthy portion of our revenue comes from sales to customers located outside of the United States. See Note 14 to the consolidated financial statements for additional information.
Backlog
We do not believe that backlog as of any particular date is indicative of future results. The majority of our quarterly silicon shipments are typically booked during the quarter. Our silicon sales are made primarily pursuant to standard purchase orders issued by OEM customers and distributors. Our eFPGA IP and design service contracts are typically made pursuant to license agreements and development contracts. Development contracts can span several months to several quarters in duration.
Competition
A number of companies offer products that compete with one or more of our semiconductor products and solutions. Competitors of our eFPGA semiconductor IP include small, venture-backed startup companies. Competitors of our low power discrete FPGA devices include suppliers of low-density FPGAs such as Lattice Semiconductor Corp. and Microsemi Corp. (a subsidiary of Microchip Technology Inc.). Competitors for our Aerospace and Defense discrete FPGAs include conventional FPGAs suppliers such as Xilinx Inc. (a subsidiary of Advanced Micro Devices, Inc.), Altera (a subsidiary of Intel Corp.), and Microsemi Corp. Competitors of our SensiML AI/ML Software business include several small, venture-backed startup companies.
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Research and Development
We are focused on developing our core programmable logic technology and software tools. Our products combine our silicon platforms with our eFPGA IP, FPGA User Tools, software drivers, and other system software, and may include SensiML software for AI applications.
Our future success will depend largely on our ability to rapidly develop, enhance, and port to new foundry and process technology our eFPGA IP solutions, as well as continue to enhance and support our FPGA User Tools to meet emerging industry standards and satisfy changing customer requirements. Further, our future success will depend on our ability to execute on current, large eFPGA IP and discrete FPGA development contracts, as well as win new ones. We have made and expect to continue to make substantial investments in R&D. Our R&D expenses were $6.4 million, or 30% of revenue, $5.0 million, or 31% of revenue, and $6.9 million, or 55% of revenue for the years ended December 31, 2023, January 1, 2023, and January 2, 2022, respectively. Research and development expenses for the year ended December 31, 2023 reflect increases in employee salary, software maintenance, and financing arrangement expenses and reductions in the allocation of R&D expenses to cost of revenues.
Manufacturing
We have close relationships with third-party manufacturers for our customer commercial products for wafer fabrication, package assembly, and testing requirements to help us ensure stability in the supply of our products and to allow us to focus our internal efforts on product and solution design and sales.
In connection with commercial customers, we outsource commercial products wafer manufacturing, primarily to GlobalFoundries and Taiwan Semiconductor Manufacturing Company Limited ("TSMC"). We outsource our commercial product packaging primarily to Amkor Technology, Inc. Integra Specialty Products, JCET Group Co. Ltd., and Golden Altos Corp. GlobalFoundries manufactures our EOS S3, EOS S3 LV, and EOS S3AI Sensor Platform in a 40 nm complementary metal oxide semiconductor ("CMOS") process, and PolarPro 3E, ArcticLink III VX and BX, and ArcticLink 3 S2 Sensor Hub, in a 65 nm CMOS process. TSMC manufactures our PASIC 3, QuickRAM and certain QuickPCI products, using a 0.35 nm CMOS process. TSMC also manufactures our Eclipse products on 0.25 micron CMOS process, and other products using a 65nm CMOS process on twelve-inch wafers. We purchase products from GlobalFoundries and TSMC on a purchase order basis.
Outsourcing of commercial wafer manufacturing enables us to take advantage of the high-volume economies of scale offered by these suppliers. We may establish additional commercial foundry relationships as such arrangements become economically useful or technically necessary.
In connection with U.S. Government end-user customers, we are required to procure wafer fabrication, package assembly, and testing from sources that maintain Defense Microelectronics Activity accreditation from the U.S. Department of Defense and maintain certain intellectual property security standards. We outsource wafer manufacturing, packaging, and testing services to certified U.S.-owned and continental U.S.-based suppliers.
Employees and Human Capital
As of December 31, 2023, we had 49 employees worldwide, of which 45 employees were located in the United States. We believe o ur future success depends in part on our continued ability to attract, hire, and retain qualified personnel. None of our employees are represented by a labor union and we believe our employee relations are favorable. We recognize that in order to drive innovation and operational excellence, we must attract, develop, motivate, and retain highly qualified talent. The well-being of employees is a key priority and includes a dynamic and welcoming workplace that promotes inclusive diversity, fosters collaboration, encourages employees to bring their best ideas to work every day, and promotes work-life balance. The principal purposes of our equity and cash incentive plans are to attract, retain, and reward personnel through the granting of stock-based and cash-based compensation awards, in order to increase shareholder value and the success of our company by motivating such individuals to perform to the best of their abilities and achieve our objectives.
As of
December 31, 2023, our research and development staff consisted of
20 employees located in California, Oregon, Texas, Utah, and Taiwan. These employees constitute the following groups:
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Our silicon engineering group develops our eFPGA IP and FPGA products.
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Our electronic design and automation software group collaborates with the open-source software community to ensure the design libraries, interface routines, and place and route software that allow our customer to take their own designs and target them to programmable hardware products are optimized. Our system software group creates the drivers and other system code required to connect our silicon hardware products to Application Processors, drivers, and microcode to support our sensor hubs.
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Our hardware group develops and verifies IP Blocks that can be programmed into our programmable logic and develops primarily open-source hardware reference designs to showcase and verify our solutions.
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Our product engineering group oversees product manufacturing and process development with our third-party foundries and is involved in ongoing process improvements to increase yields and optimize device characteristics.
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The office of the CTO investigates future trends and requirements in order to define the next generation of solutions and platforms.
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Our SensiML group develops and maintains all software with respect to the SensiML Analytics Software Suite.
We monitor employee turnover rates by region and globally. Approximately 34% of our employees have been employed by us for more than 10 years and approximately 20% have been employed by us for more than 20 years. The average tenure is 9.65 years. Our turnover rate was 14% for the fiscal year ended December 31, 2023. We believe our compensation philosophy, along with the career growth and development opportunities promotes longer employee tenure and reduces voluntary turnover.
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Intellectual Property
We believe that it is important to maintain a large patent portfolio to protect our innovations. We currently hold 21 active U.S. patents and have five pending applications for additional U.S. patents. Our patents contain claims covering various aspects of programmable integrated circuits, programmable interconnect structures, and programmable metal hardware products. In Europe and Asia, we hold five patents and have zero pending applications . Our issued patents expire between 2026-2042.
I n most cases, revenue will decline from a decrease in demand for our mature products long before the expiration of pending or issued patents relating to the underlying technology in such products. The decision to cease maintaining a patent is made based on the importance of the patent in our current or future product offerings.
We have five registered trademarks with the U.S. Patent and Trademark Office.
With regard to certain patents, the U.S. Government has an irrevocable, non-exclusive, royalty-free license, pursuant to which the U.S. Government may use or authorize others to use the inventions covered by such patents.
Information About Our Executive Officers and Directors
Our executive officers are appointed by, and serve at the discretion of, our Board of Directors. There are no family relationships among our directors and officers.
The following table sets forth certain information concerning our current executive officers and directors as of March 26, 2024:
Name
Age
Position
Brian C. Faith
49
President and Chief Executive Officer; Director
Elias Nader
59
Chief Financial Officer and Senior Vice President (SVP) of Finance
Rajiv Jain
63
Vice President, Worldwide Operations
Timothy Saxe
68
Senior Vice President Engineering and Chief Technology Officer
Owen Bateman
57
Vice President, Worldwide Sales
Michael R. Farese
77
Chairman of the Board
Joyce Kim
53
Director
Radhika Krishnan
53
Director
Andrew J. Pease
73
Director
Christine Russell
74
Director
Gary H. Tauss
69
Director
Brian C. Faith joined QuickLogic in June 1996. Mr. Faith has served as our President and Chief Executive Officer since June 2016 after having served as Vice President of Worldwide Marketing and Vice President of Worldwide Sales & Marketing between 2008 and 2016. Mr. Faith during the last 25 years has held a variety of managerial and executive leadership positions in engineering, product line management, marketing and sales. Mr. Faith has also served as the board member of the Global Semiconductor Alliance (GSA), the Chairman of the Marketing Committee for the CE-ATA Organization. He holds a B.S. degree in Computer Engineering from Santa Clara University and was an Adjunct Lecturer at Santa Clara University for Programmable Logic courses.
Elias Nader joined QuickLogic in February 2022. Mr. Nader brings more than 30 years of experience in semiconductors and related industries, including 20 years in senior leadership positions. Prior to joining QuickLogic, Mr. Nader most recently served as Senior Vice President and Chief Financial officer at Pixelworks, Inc., where he was directly responsible for all of General and Administrative worldwide and worked directly with the Board of Directors to provide strategic and operational direction to the company. Prior to that, Mr. Nader worked at Sigma Designs, Inc. as the Senior Vice President, Chief Financial Officer and Corporate Secretary. Mr. Nader has also served in executive capacities at Imperial Jet and Dionex Corp. Mr. Nader holds a Bachelor of Science Degree in Accounting and Bachelor of Arts Degree in Economics and an MBA in International Business from San Jose State University.
Rajiv Jain joined QuickLogic in August 1992. Mr. Jain has served as our Vice President of Worldwide Operations since April 2014. Prior to this role, Mr. Jain served as QuickLogic’s Senior Director of Operations and Development Engineering from 2011 to 2014, Senior Director of System Solutions and Process Technology from 2009 to 2011, Director of Process Technology from 1997 to 2009, and Senior Process Technologist from 1992 to 1997. Prior to joining QuickLogic, Mr. Jain was a Senior Yield Engineer at National Semiconductor from 1991 to 1992, where he focused on BiCMOS product yield improvements, and at Monolithic Memories from 1985 to 1988, where he focused on BiPolar product yield and engineering wafer sort improvements. Mr. Jain holds a Master’s degree in Chemical Engineering from the University of California, Berkeley and a B.S. degree in Chemical Engineering from the University of Illinois, Champaign/Urbana.
Owen Bateman joined QuickLogic in February 1997. Mr. Bateman has served as our Vice President of Worldwide Sales since April 2022. Prior to this role, Mr. Bateman served as QuickLogic’s Senior Director of Sales EMEA and USA from 2013 to 2022, and Strategic Accounts, Direct Sales and Channel Sales from 1997 to 2013. Prior to joining QuickLogic, Mr. Bateman held sales and field application engineering positions at Intel and Abacus Polar. Mr. Bateman has designed FPGAs and completed several successful FPGAs and custom ASIC designs. Mr. Bateman holds a Higher National Certificate in Electronic and Microelectronic Engineering from Brooklands College, England.
Timothy Saxe (Ph.D.) joined QuickLogic in May 2001. Dr. Saxe has served as our Senior Vice President of Engineering and Chief Technology Officer since August 2016 and Senior Vice President and Chief Technology Officer since November 2008. Previously, Dr. Saxe has held a variety of executive leadership positions in QuickLogic including Vice President of Engineering and Vice President of Software Engineering. Dr. Saxe was Vice President of FLASH Engineering at Actel Corp. a semiconductor manufacturing company, from November 2000 to February 2001. Dr. Saxe joined GateField Corp., a design verification tools and services company formerly known as Zycad, in June 1983 and was a founder of their semiconductor manufacturing division in 1993. Dr. Saxe became GateField’s Chief Executive Officer in February 1999 and served in that capacity until Actel Corp. acquired GateField in November 2000. Dr. Saxe holds a B.S.E.E. degree from North Carolina State University, and an M.S.E.E. degree and a Ph.D. in Electrical Engineering from Stanford University.
Information regarding the backgrounds of our directors is hereby incorporated by reference from our definitive Proxy Statement relating to the 2024 Annual Meeting of Stockholders, which Proxy Statement is anticipated to be filed within 120 days after the end of the Fiscal Year covered by this Annual Report.
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