Item 1. Business
Item 1.
Business
Company Overview
We are engaged in the business
of developing, commercializing and licensing proprietary processes and technologies for the $550+ billion semiconductor industry. Our
lead technology, named Mears Silicon Technology™, or MST ® , is a thin film of reengineered silicon, typically 100
to 300 angstroms (or approximately 20 to 60 silicon atomic unit cells) thick. MST is our proprietary and patent-protected performance
enhancement technology that we believe addresses a number of key engineering challenges facing the semiconductor industry. We believe
that by incorporating MST, transistors can be made smaller, with increased speed, reliability and power efficiency. In addition, since
MST is an additive and low-cost technology, we believe it can be deployed on an industrial scale, with machines commonly used in semiconductor
manufacturing. We believe that MST can be widely incorporated into the most common types of semiconductor products, including analog,
logic, optical and memory integrated circuits.
We do not design or manufacture
integrated circuits directly. Instead, we develop and license technologies and processes that we believe offer the designers and manufacturers
of integrated circuits a low-cost solution to the industry’s need for greater performance and lower power consumption. Our customers
and partners include:
·
foundries, which manufacture integrated circuits on behalf of fabless manufacturers;
·
integrated device manufacturers, or IDMs, which are the fully-integrated designers and manufacturers of integrated circuits;
·
fabless semiconductor manufacturers, which are designers of integrated circuits that outsource the manufacturing of their chips to foundries;
·
original equipment manufacturers, or OEMs, that manufacture the epitaxial, or epi, machines used to deposit semiconductor layers, such as the MST film, onto silicon wafers; and
·
electronic design automation companies, which make tools used throughout the industry to simulate performance of semiconductor products using different materials, design structures and process technologies.
Our principal business objective
is to enter into commercial license agreements that enable our customers to manufacture and sell MST-enabled products, generating license
revenues and ongoing royalties. We also license our MSTcad ® software to customers, enabling them to simulate the effects
of MST on their products using Synopsys, Inc.’s technology computer-aided design, or TCAD, software. In addition, we offer fee-based
engineering services to customers evaluating MST. Our goal is that MSTcad licensing and engineering service arrangements will be tools
that demonstrate the benefits of MST and will lead customers to enter into full commercial licenses. A “full commercial license”
involves a three-stage approach consisting of:
1.
An integration license that provides our customer the right to use MST technology (with MST film deposited for the customer by Atomera) in the manufacture of silicon wafers for internal testing and sampling;
2.
An R&D license, which includes the rights granted in an integration license and grants our customer the rights to install MST on a tool in their fab and to manufacture MST-enabled products for internal use only; and
3.
A high-volume manufacturing, or HVM, license which grants the rights to manufacture and sell MST-enabled products to their customers.
In 2024, we changed the terminology
of our licenses. Previously, our R&D license was referred to as a “manufacturing license” and our HVM license was called
a “distribution license.” However, the rights conferred to customers under each of these licenses did not change and the terms
are used interchangeably in this Annual Report.
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Depending upon our customers’
business needs and how we initially engaged with them, we may make these license grants in one or more separate contracts. The upfront
license fee becomes larger at each stage. Upon the grant of an HVM license, our licensees are also required to make royalty payments to
us based on the number and/or sales price of MST-enabled products they sell to their customers either at the wafer or individual chip
level. We have engaged with certain customers under joint development agreements, or JDAs. Our JDAs include development, technology transfer,
manufacturing and licensing components.
To date, applications of our MST
technology have primarily been for power devices, RFSOI devices and advanced CMOS integrated circuits including logic and memory. CMOS
integrated circuits are the most widely used type of integrated circuits in the semiconductor industry. We believe MST has the potential
to overcome the key challenges found in the implementation of next-generation nano-scale semiconductor devices incorporating CMOS type
transistors, namely enhancing drive current, reducing leakage and reducing variability. In addition, we believe that MST has the potential
to deliver these benefits through a single technology that requires relatively minor modifications to the industry-standard CMOS manufacturing
flow. Consequently, we believe that by incorporating MST, designers can make transistors with increased speed, reliability and energy
efficiency, without significantly altering the current fabrication process or cost of production.
During 2024, we began applying
our technology to wafers used for fabrication of “compound semiconductors” which are devices built using materials other than
silicon, such as gallium nitride (GaN), which have properties especially attractive to the power and radio frequency markets. Currently,
materials such as GaN suffer from a tradeoff between high-cost specialized wafers and defective, low-yielding wafers resulting from the
crystal mismatch between heterogeneous materials. We believe MST can offer a cost-effective solution to these tradeoffs by serving as
a buffer layer between different materials, such as GaN and a silicon wafer substrate.
We were organized as a Delaware
limited liability company under the name Nanovis LLC on November 26, 2001. On March 13, 2007, we converted to a Delaware corporation under
the name Mears Technologies, Inc. On January 12, 2016, we changed our name to Atomera Incorporated. Shares of our common stock are listed
on the NASDAQ Capital Market under the symbol “ATOM”.
Industry Overview
Semiconductors, Generally
Recent years have seen a remarkable
proliferation of consumer and commercial products, especially in wireless, automotive and high-speed devices. Cloud computing and artificial
intelligence technologies have provided people with new ways to create, store and share information. At the same time, the increasing
use of electronics in cars, buildings, appliances and other consumer products is creating a broad landscape of “smart” devices
such as wearable technologies and The Internet of Things. Artificial Intelligence (AI) is being widely adopted by both the enterprise
and consumer, and the infrastructure required for the processing of AI workloads is considerable. The COVID-19 pandemic accelerated trends
toward remote and hybrid work, cloud computing and mobile devices. These trends coincided with the increasing rollout of 5G cellular networks
and associated devices, augmented and virtual reality technologies, cryptocurrencies, and especially artificial intelligence technology,
all of which require high levels of processing power. These trends in both enterprise and consumer applications are driving increasing
demand for integrated circuits and systems with greater functionality and performance, reduced size, and much less power consumption as
key requirements.
These developments depend, in
large part, on integrated circuits, or microchips, which are sets of electronic circuits on a single chip of semiconductor material, normally
silicon. It is common for a single semiconductor chip to combine many components (processor, communications, memory, custom logic, input/output)
resulting in highly complex chip designs. Transistors are the building blocks of integrated circuits and the most complex semiconductor
chips today contain more than 100 billion transistors, each of which may have features that are much less than 1/1,000 th the
diameter of a human hair.
The most widely used transistors
in semiconductor chips today are based on CMOS technology. Among its many attributes, CMOS allows for a higher density of transistors
on a chip and lower power usage than non-CMOS technologies.
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The Pursuit of Increased Semiconductor Performance
For years, the semiconductor industry
was able to almost double the number of transistors it could pack into a single microchip about every two years, a rate of improvement
commonly known as “Moore’s Law.” The semiconductor industry uses the term “node” to describe the minimum
line width or geometry on a semiconductor chip, expressed in nanometers, or nm, for today’s technologies. Historically, smaller
nodes enable more densely packed designs that produced less costly products on a per-transistor basis. Frequently, smaller nodes also
correspond to an improvement in chip performance, making them the mile markers of Moore’s Law, with each node marking a new generation
of chip-manufacturing technology.
Until recently, the industry succeeded
at maintaining the rate of improvement predicted by Moore’s Law by scaling the key transistor parameters, such as shrinking feature
sizes and reducing operating voltages, thereby allowing more transistors to be packed onto a single microchip. This trend was facilitated
in large part by the development of CMOS technologies and rapid improvements in in lithography, which is the technology used in patterning
circuits. However, a discontinuity in the rate of improvement delivered by scaling appeared when transistor technology reached feature
sizes below 100 nanometers. The industry responded with advanced materials to supplement the ongoing geometry shrinks. Some of those materials
advances included strained silicon, Silicon-on-Insulator and High-K/Metal Gate. Semiconductor makers also attempted to obtain performance
improvements through more exotic design architectures which frequently required material innovations to support their manufacturability
and reliability.
The designers and manufacturers
of integrated circuits and systems — our targeted customers — are facing intense pressure to deliver innovative products while
constantly reducing their time-to-market and prices. In other words, innovation in chip and system design today often hinges on “better,
sooner and cheaper.” We believe that the semiconductor industry has accepted that moving forward in the nano-era will require adoption
of new innovations that extend the scaling formula, including those based on the use of new engineered materials, a market opportunity
our MST technology seeks to address. Because shrinking geometries at the smaller nodes incurs higher capital and manufacturing costs,
only a limited number of companies can afford to continue investing in those nodes. These constraints have caused semiconductor designers
and manufacturers to increasingly rely on engineered materials, like MST, to deliver node-over-node increases transistor performance without
having to rely solely on dimensional (lithographic) feature scaling..
Vertical Disaggregation of the Industry
In trying to keep research and
development costs manageable, while attempting to satisfy the demand for increasingly complex semiconductors, certain designers and manufacturers
of integrated circuits have transitioned to a more open innovation model in which competing companies and third-party providers actively
collaborate to address performance issues through various alliances, joint ventures, and licensing of externally developed technology.
Historically, most semiconductor
companies were vertically integrated. They designed, fabricated, packaged and tested their semiconductors using internally developed software
design tools and manufacturing processes and equipment. As the cost and skills required for designing and manufacturing complex semiconductors
have increased, the semiconductor industry has become disaggregated, with companies concentrating on one or more individual stages of
the semiconductor development and production process. This disaggregation has fueled the growth of fabless semiconductor companies, design
tool vendors, semiconductor equipment manufacturers, third-party semiconductor manufacturers (or foundries), semiconductor assembly, package
and test companies, and intellectual property companies that develop and license technology to others.
While specialization has enabled
greater development and manufacturing efficiency, it has also created an opportunity for licensing companies, such as Atomera, that develop
and license technology to meet fundamental, industry-wide challenges. These intellectual property companies have been able to gain broad
adoption of their technology throughout the industry by working with companies within the semiconductor supply chain to evaluate and integrate
their technology. Manufacturers and designers of semiconductors increasingly find it more cost-effective to license technologies from
IP-based companies than to develop processes internally that are not their core competence. We believe this collaboration and integration
of externally-developed IP benefits semiconductor companies by enabling them to bring new technology to market faster and more cost-effectively.
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Applications of Mears Silicon Technology
Among the initial applications
for which MST can provide technology differentiation are in power devices, RFSOI devices and advanced CMOS integrated circuits. We offer
MST-SP (between 3-5 volts) and MST-SPX (up to 48V), which are types of MST-enabled power devices that offer what we believe to be industry-leading
on-resistance (also referred to as Rsp) at comparable or improved breakdown voltage and reliability metrics, enabling reduced footprint
(and thus smaller devices). We believe that the MST-SP and MST-SPX devices will have immediate application in power management integrated
circuits (or PMICs) which are pervasive in hand-held, battery-powered devices and elsewhere. The higher voltage MST-SPX devices are applicable
to the rapidly growing automotive and data center power sectors. Both of these MST solutions fill a growing need for reducing power consumption
and improving energy efficiency.
We believe MST has the potential
to overcome the key challenges found in the implementation of next generation nano-scale semiconductor devices incorporating CMOS-type
transistors, namely enhancing drive current, reducing leakage and reducing variability. Shown in the diagram below are two illustrative
implementations of MST in advanced CMOS transistors. The first incorporates MST into the channel region of the transistor which can help
to reduce gate leakage (translates to lower off-state power consumption) while the second shows MST incorporated into the source/drain
region of the transistor. This latter implementation helps control dopant diffusion into the channel which improves control of how the
transistor turns on and the variability of the transistor operation. In addition, we believe that MST has the potential to deliver these
benefits through a single technology that requires relatively minor modifications to industry-standard CMOS manufacturing flows. Consequently,
we believe that by incorporating MST, designers can make transistors with increased speed, reliability and energy efficiency, without
significantly altering the current fabrication process or cost of production. These improvements are increasingly difficult to achieve
and important in next generation logic and memory devices.
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MST improvements are delivered
through our proprietary and patent-protected approach based on a deep understanding of the physics of modern semiconductor devices. Our
MST film can be used to create better controlled doping profiles for a wide variety of semiconductor device designs, including junctions,
contacts and channel regions. MST can thus enable more optimized device designs with improved current and voltage handling, lower variability
and improved yield.
We believe the enhancements enabled
by MST, as demonstrated in simulations and on our own and our customers’ test chips, are approximately equivalent to the enhancements
enabled by one-half to a full node of improvement and, therefore, can extend the productive life of capital equipment and wafer fabrication
facilities. The extent of MST-enabled enhancement depends on the device technology and application. We believe that MST compares favorably
to other alternatives for enhancing performance of CMOS-type transistors and is both compatible with technologies such as strained silicon
and HKMG.
Given the costs of moving to more
advanced technologies, we believe one of the most compelling aspects of MST is its cost/benefit profile. We believe that MST will provide
a lower cost of production due to our technology’s potential to reduce die size while leveraging existing manufacturing tools, thereby
providing chip makers with increased performance at all process nodes with significantly fewer disruptions to manufacturing processes
and less incremental cost than other advanced technologies.
We believe MST can improve transistor
performance in a variety of device types including microprocessors; logic products; analog, RF, and mixed-signal devices; as well as DRAM,
SRAM, and other memory integrated circuits. We have therefore developed different MST product options that can be applied to the critical
industry segments and technology nodes. As of the date of this Annual Report, we have done technology simulation work with universities
and leading industry players at nodes from 180nm to 2nm. We have also simulated devices with leading industry research facilities and
built (and electrically verified) test chips using MST in customer manufacturing facilities which have produced results that demonstrate
many of the benefits described above.
Development Partnerships
Synopsys . Since 2017 we
have worked in collaboration with Synopsys, Inc., a provider of the most broadly used TCAD simulation software in the semiconductor industry.
As a result of our collaboration, Synopsys’ software now supports modeling of MST, which enables semiconductor manufacturers and
designers to model the interaction of MST with other process steps. In December 2020, we announced availability of our MSTcad software
which runs on Synopsys’ Sentaurus TCAD software and enables semiconductor engineers to simulate the benefits of integrating MST
in a variety of devices. We continually refine our MSTcad software by calibrating our models against measured silicon results and we regularly
release updates to that software. We believe these capabilities are helping us focus integration efforts for potential customers more
quickly on those areas most likely to deliver benefits, thus shortening test cycles and, we believe, accelerating the time to a license
decision. In the last three years, semiconductor fabs have generally been running at high capacity to keep up with industry supply shortages
which has made it challenging for us to run wafers through our customers’ fabrication lines. MSTcad has been increasingly used by
existing and potential customers to identify applications where MST can have the greatest benefit, without requiring access to customer
fabs.
Epi Tool Lease. In August
2021 we entered into a five-year lease for an Applied Materials Centura epitaxial deposition reactor which handles both 200mm and 300mm
wafers. We utilize this tool to perform deposition on both customer and internal R&D wafers. The terms of our tool lease include the
lessor’s maintenance and support as well as access to a cleanroom with advanced cleaning and inspection tools.
MST Commercialization
We do not intend to design or
manufacture integrated circuits directly. Instead, we develop and license technologies and processes that offer the designers and manufacturers
of integrated circuits increased performance at a lower cost than currently available alternatives. Our customers and partners include
foundries, integrated device manufacturers, or IDMs, fabless semiconductor manufacturers, OEMs that manufacture epitaxial deposition tools
(also known as epi machines), and electronic design automation software companies, such as Synopsys.
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Our business model is to enter
into licensing arrangements whereby foundries and IDMs pay us a license fee for their use of MST technology in the manufacture of silicon
wafers as well as a royalty for each product. Depending on our customer’s business model and the negotiated terms of our license
agreements with each customer, those royalties may be calculated on the basis of wafers or products manufactured and sold that incorporate
MST. The primary beneficiaries of our commercialization activities are the IDMs and fabless semiconductor manufacturers, as they produce
and distribute integrated circuit devices which are enhanced when they incorporate MST technology. The foundries and OEMs also play an
important role in our commercialization strategy because these parties traditionally seek to provide new and improved technologies to
their customers – the fabless semiconductor manufacturers in the case of the foundries, and the IDMs and foundries in the case of
the OEMs.
In the semiconductor industry,
new technologies are vetted thoroughly and carefully by early adopters who are trying to achieve differentiation over competitors. After
the early adopters prove the technology in production, it then tends to be broadly and relatively quickly adopted by “followers”
who need to overcome their competitive disadvantage. Due to the cost and complexity of semiconductor manufacturing processes and the desire
to maintain a stable and repeatable process flow, new technologies tend to be adopted broadly by the industry and, wherever possible,
exploited for several generations until they are fully optimized and adoption costs are fully absorbed.
Although each customer or potential
customer follows an evaluation and adoption model that is particular to its business model and product focus, our engagements generally
consist of the following phases:
1.
Engineering Planning: In this phase we engage in a technical exchange of information under a non-disclosure agreement to understand the customer’s manufacturing process and to determine how best to integrate the deposition of MST film onto the customer’s semiconductor wafers.
2.
Set-up for MST Integration: We agree upon the technical evaluation details, including the expected rounds of evaluation testing, the parameters to be tested and allocation of costs. Customers provide us with wafers for our internal processing and physical characterization. Some customers work together with us to develop a TCAD model showing possible results of MST integration with their particular manufacturing process.
3.
MST Integration. Typically, this phase includes several rounds of tests that involve building test devices on a semiconductor wafer using our MST technology within the customer’s manufacturing process flow. In this phase, we perform the MST deposition on customer wafers, so wafers must be shipped back and forth between the customer and Atomera. We believe that this phase will continue to be the longest in our customer engagement process because integrating into a customer’s flow frequently requires us to conduct subsequent tests based on the result of earlier test runs. This phase also requires investment of time and resources by customers. In order to progress beyond this phase, we must demonstrate benefits at a commercially significant level. It is difficult for both customers and for Atomera to estimate the amount of time a customer will be in the integration phase.
4.
Process Installation . Prior to enabling a customer to install and use MST technology on epitaxial deposition machines in their own fab, we require execution of an R&D license which grants rights limited to manufacturing MST-enabled products for internal R&D and qualification but does not give the customer the right to distribute or sell products that use MST. After installation of MST into the fab, the customer will continue development work to perfect the integration of MST technology into their transistor manufacturing process flow. Upon completion the customer will typically release a new Process Design Kit (PDK) which incorporates MST. Circuit designers will use the new PDK when developing new microchips for production.
5.
Technology qualification . The customer will conduct additional testing to ensure that the new products developed with the new PDK achieve manufacturing reliability under accelerated test conditions that simulate volume production. Upon successful completion of the qualification phase and execution of a high volume manufacturing (HVM) license with Atomera, products can be built and shipped using this manufacturing process.
6.
Production . Upon commencement of sales of wafers or devices built using MST, our customer will pay us a royalty that will be a percentage of the selling price of the wafer or device, depending on the terms agreed in the applicable license agreement.
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While the above steps describe
a model customer engagement, we have engaged with some customers in ways that do not follow this precise order. JDAs are an example of
an engagement format that may combine engineering service, development, manufacturing, process optimization and other joint activities
that do not follow the order described above. In addition, we may from time to time enter into evaluation license agreements with certain
customers under which they may install MST in their fabs to run internal tests only and not for commercial use or distribution. Other
potential customers may run tests on wafers containing MST prior to further engagement with us to integrate MST into their manufacturing
process.
We believe that our success is
dependent upon the adoption of our MST technology through to commercial production by at least one IDM, foundry, or fabless semiconductor
manufacturer. As of the date of this Annual Report, MST was in the integration phase (Phase Three as described above) on 14 different
engagements and two engagements in Phase Four (process installation). One of these Phase Four customers is ST Microelectronics (“ST”),
our first customer to sign a full commercial license.
We are also working with OEMs
on process development and equipment optimization to ensure that MST can be reliably and predictably deposited using their manufacturing
tools. We have successfully deposited MST using tools made by each of the leading epitaxial deposition equipment suppliers and we believe
that if we are successful in our commercialization efforts, these tool OEMs will promote the incorporation of our MST technology as an
option to their standard offering. By doing so, we believe they will simultaneously stimulate additional sales of their capital equipment
and encourage more customers to adopt MST.
Through our collaboration with
Synopsys, we enable potential customers of MST to more quickly assess the potential benefits of MST to their semiconductor devices. By
creating TCAD software models, we can work with manufacturers to assess which of their product types would most benefit from MST. We believe
this modeling capability has shortened the time required for us to engage with new potential customers and should ultimately lead to a
faster decision process by the customer regarding licensing MST.
We market our MST technology directly
to the semiconductor industry through our significant industry contacts and relationships. We also sponsor academic research and participate
in industry conferences and associations. In certain foreign jurisdictions, we engage sales representatives to assist us in establishing
relationships with local customers.
Customers
In April 2023, we entered into
a license agreement with ST that authorizes them to manufacture and distribute MST-enabled products to its customers. This agreement provides
for payment of license fees payable upon reaching milestones consistent with Atomera’s standard business model. Our standard model
is based around two major milestones, namely the installation of MST in a customer’s fab and qualification of an MST-enabled process.
Our license agreement with ST is our first grant of commercial manufacturing and distribution rights. In the fourth quarter of 2023, we
completed the first major milestone under the ST license agreement by delivering our MST film recipe and ST accepting the film, resulting
in our recognizing license revenue associated with that milestone. ST is currently performing testing to optimize their integration of
MST as part of their qualification process. Upon qualification, we will earn additional license fees for the distribution license (which
we now refer to as the HVM license), after which ST will be entitled to commercially manufacture and sell MST-enabled products and royalties
will be payable to us for every product sold. There can be no assurance, however, that ST will complete its process qualification and
pursue the licensed rights through to the commercial manufacture and sale of MST-enabled products.
We have two JDAs in place. The
first is with a leading semiconductor provider for integration of our MST technology into their manufacturing process. Under this JDA,
we granted our customer a paid manufacturing license pursuant to which the customer installed the recipe for our MST film into a tool
in their fab and was authorized to fabricate semiconductor wafers incorporating MST for internal use, resulting in this customer entering
Phase Four. This JDA also included development milestones that we achieved. We continue to work with this customer and, although this
JDA does not confer commercial distribution rights, we believe that successful achievement of the JDA milestones is a significant step
toward commercialization, as it should facilitate progress toward integrating MST into one or more of our customer’s multiple production
lines, each of which can provide license revenues and royalty streams. We also executed a JDA with a major semiconductor foundry which
contains technical targets which, if achieved, should result in paid licenses and engineering services revenue. As of the date of this
Annual Report, we are actively engaged with this second JDA customer and planning additional development and integration work that, if
successful we believe would be a significant step toward commercialization.
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We have also entered into integration
license agreements with (i) a leading fabless RF semiconductor provider, (ii) a semiconductor foundry and (iii) Asahi Kasei Microdevices,
or AKM, which is an IDM and fabless vendor. Under these integration license agreements, customers have paid us for the right to evaluate
MST technology, which is integrated onto their semiconductor wafers. We deposit MST onto the customers’ wafers and the customer
has the right under the license agreement to complete the manufacturing process, which enables them to evaluate our technology and to
provide limited samples to their customers. AKM, our fabless licensee and our foundry licensee are in our Phase Three (MST Integration).
We intend that each of our integration
license agreements and JDAs will result in full commercial licenses like our license agreement with ST which provides for substantially
larger upfront license fee payments for grants of manufacturing and distribution rights than the integration licenses and will require
royalty payments to us based on sales of MST-enabled products they sell to their customers. However, our ability to enter into royalty-based
manufacturing and distribution agreements with licensees under our integration license agreements and JDAs will depend, in large part,
on the performance of devices they build using MST and the successful integration of our MST technology on a high-volume production scale.
There can be no assurance that our MST technology will deliver the performance, power, cost reduction or other requirements our customers
seek for their products or that the integration of our technology with our customers’ manufacturing process will be successful in
high volume. In addition, even if our MST technology meets our customers’ technical objectives one or more of our licensees may
decide, for reasons unrelated to the price or performance of our MST technology, not to enter into manufacturing and distribution license
agreements.
Competition
Our lead product, MST, is a proprietary
and patent-protected performance enhancement technology that we believe addresses a number of key engineering challenges facing the semiconductor
industry. Historically, the development of a new material technology for the semiconductor industry has taken 10-20 years from conceptualization
to volume production. Atomera’s MST technology has followed a similar trajectory, from early patents, publications and presentations
to the industry to early evaluations and installation at customers.
We compete with IDMs, OEMs, foundries,
fabless manufacturers of semiconductors and semiconductor IP licensing companies for the development and commercialization of technologies
that improve the performance of semiconductors. Historically, when a new fabrication process proves to be a low-cost improvement to the
standard fabrication process, and is additive, rather than in place of other performance technologies, it has been successfully adopted
industry wide. Good examples of such advances have been chemical mechanical polishing (or CMP), strained silicon and High-K/Metal-Gate.
The cost to develop such solutions is typically very high and requires many years of testing and modification to perfect. MST has gone
through this long, expensive development period and therefore we believe that it has the potential to be one of these low-cost additive
technologies, in which case MST would not be subject to significant direct competition from other technologies. We are not aware of another
technology being offered in the market which provides the same technical benefits as MST. Nevertheless, in some cases the engineering
teams in our customers, who are developing their own process improvements, may view MST as competition to their internally-developed solutions.
Likewise, third parties like equipment OEMs, universities, or other material providers may offer solutions which have some of the same
benefits that MST offers. We believe that our technology has far more effective, well-developed and fully-supported performance improvements
than those offered by these third parties.
Research and Development
The principal focus of our research
and development efforts is on enabling existing and prospective customers to integrate MST into their manufacturing processes and enable
them to commercialize MST-enabled semiconductor products. We also dedicate research and development resources to evolving and expanding
our technology to address new process technologies in the semiconductor industry roadmap. Our research and development is conducted internally,
but we work closely with third parties in the semiconductor industry to evaluate and qualify our technology for incorporation into semiconductor
products and fabrication equipment. During the years ended December 31, 2024 and 2023, we incurred research and development expenses of
approximately $11.0 million and $12.5 million, respectively.
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We believe that our success depends
in part on our ability to achieve the following in a cost-effective and timely manner:
·
enable customers to integrate MST into their products;
·
develop new technologies that meet the changing needs of the semiconductor industry;
·
improve our existing technologies to enable growth into new application areas; and
·
expand our intellectual property portfolio.
Intellectual Property Rights
We regard the protection of our
technologies and intellectual property rights as an important element of our business operations and crucial to our success. We rely primarily
on a combination of patent laws, trade secret laws, confidentiality procedures, and contractual provisions to protect our proprietary
technology. We require our employees, consultants, and advisors to enter into confidentiality agreements. These agreements provide that
all confidential information developed or made known to the individual during the course of the individual’s relationship with us
is to be kept confidential and not disclosed to third parties except under specific circumstances. In the case of our employees and consultants,
the agreements provide that all of the technology that is conceived by the individual during the course of employment is our exclusive
property. The development of our technology and many of our processes are dependent upon the knowledge, experience, and skills of key
scientific and technical personnel.
As of December 31, 2024, we have
been granted 108 patents in the U.S. and 112 abroad and we have 50 pending patent applications in the U.S. and 77 abroad. We believe our
patents adequately block competitors from using our MST technology without our approval and our patent activity over the past five years
has focused on extending the scope of our portfolio through a variety of means, including but not limited to patenting new structures,
materials and methods uniquely enabled by MST technology. In addition, our MST film recipe is confidential know-how, which is only disclosed
to customers who have been, at a minimum, a manufacturing licensee and who have executed the appropriate legal agreements. Unlike patents,
know-how has no expiration and our film recipe is necessary in order to utilize MST technology. However, there can be no assurance that
one or more of our patents would survive a legal challenge to their scope, validity, or enforceability, or provide significant protection
for us. Protection of our film know-how depends on our licensee’s compliance with the terms of their contracts including non-disclosure
provisions thereof. The failure of our patents, or the failure of trade secret laws, to adequately protect our technology, might make
it easier for our competitors to offer similar products or technologies or for our potential customers to build products with methods
and materials similar to MST without paying us a license fee. In addition, patents may not issue from any of our current or future applications.
We also hold registered trademarks
in the United States for the marks “Atomera,” “MST” and “MSTcad” and in China for the mark “Mears”.
Employees and Human Capital Management
As of the date of this Annual
Report, we employ 20 people on a full-time basis.
Our human capital resources objectives
include, as applicable, identifying, recruiting, retaining, incentivizing and integrating our existing and new employees. The principal
purposes of our equity incentive plans are to attract, retain and reward personnel through the granting of stock-based compensation awards
that align their compensation with our business objectives and with creation of shareholder value.
Available Information
Our website is located at www.atomera.com.
The information on or accessible through our website is not part of this Annual Report on Form 10-K. Copies of our Annual Reports on Form
10-K, Quarterly Reports on Form 10-Q, Current Reports on Form 8-K and amendments to these reports filed or furnished pursuant to Section
13(a) or 15(d) of the Exchange Act are available free of charge, on our investor relations website as soon as reasonably practicable after
we file such material electronically with or furnish it to the Securities and Exchange Commission, or the SEC. A copy of this Annual Report
on Form 10-K is also located at the SEC’s Public Reference Room at 100 F Street, NE, Washington, D.C. 20549. Information on the
operation of the Public Reference Room can be obtained by calling the SEC at 1-800-SEC-0330. The SEC also maintains an internet site that
contains reports and other information regarding our filings at www.sec.gov.
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