What changed in this filing

/stocks — the workspaceLOADING

Item 1. Business

2026-03-02 compared with 2025-03-03 · 73 added, 200 removed, 158 unchanged (63% of the section changed)

We supply advanced, innovative capital equipment developed for the global semiconductor industry.

Fabricators of advanced integrated circuits, or chips, can use our wet-cleaning and other front-end processing tools in numerous steps to improve product yield, even at increasingly advanced process nodes.

We have designed these tools for use in fabricating foundry, logic and memory chips, including dynamic random-access memory, or DRAM, and 3D NAND-flash memory chips.

We also develop, manufacture and sell a range of advanced packaging tools to wafer assembly and packaging customers.

Our products are designed to address yield-critical and performance-sensitive process steps that become increasingly difficult as semiconductor devices scale to smaller geometries and more complex structures.

We focus on developing differentiated process solutions that enable effective particle removal, uniform material deposition, and reliable process control, while helping customers manage cost of ownership, throughput, and environmental considerations.

We believe this approach has supported broader adoption of our tools across multiple technology nodes and device types.

Fabricators of advanced integrated circuits, or chips, can use our wet-cleaning, plating, furnace, PECVD, track, and other front-end processing equipment in numerous steps to improve product yield, even at increasingly advanced process nodes.

We have designed these products for use in fabricating foundry, logic and memory chips, including dynamic random-access memory, or DRAM, and 3D NAND-flash memory chips.

We also develop, manufacture and sell a range of advanced packaging equipment to wafer assembly and packaging customers.

Revenue from single wafer cleaning, Tahoe and semi-critical cleaning equipment totaled $626.0 million, or 69.5% of total revenue in 2025, $578.9 million, or 74.0% of total revenue in 2024, and $403.9 million, or 72.4% of total revenue in 2023.

5 unchanged sentences

Gartner estimates the total worldwide semiconductor WFE market grew by 11.0% from $111.6 billion in 2024 to $123.9 billion in 2025, and estimates will increase by 11.8% to $138.5 billion in 2026.

Gartner estimates China WFE grew by 11.5%, from $33.7 billion in 2023 to $37.5 billion in 2024, and is expected to decrease by 23.6% to $28.7 billion in 2025 1 .

Gartner estimates China WFE decreased by 1.7%, from $40.0 billion in 2024 to $39.3 billion in 2025, and is expected to decrease by 9.9% to $35.4 billion in 2026 1 .

We have focused our selling efforts o n establishing a referenceable base of leading foundry, logic and memory chip makers, whose use of our products can influence decisions by other manufacturers.

We believe this customer base has helped us penetrate the mature chip manufacturing markets and build credibility with additional industry leaders.

We have used a “demo-to-sales” process to place evaluation equipment, or “first tools,” with a number of selected customers.

We have used a “demo-to-sales” process to place evaluation equipment, or “first tools,” with numerous selected customers.

To date, a substantial majority of our sales of semiconductor capital equipment have been to customers located in Asia, and we anticipate that a substantial majority of our revenue from these products will continue to come from customers located in this region for the foreseeable future.

Our operation includes sales, marketing and services personnel in North America, Western Europe and Southeast Asia to expand and support major new customer initiatives for the products of ACM Shanghai to additional regions beyond mainland China.

We are focused on building a strategic portfolio of intellectual property to support and protect our key innovations.

Our tools have been developed using our key proprietary technologies:

1 The information contains statistical data and estimates, including forecasts, that are based on information provided by Gartner®, "Forecast:

Semiconductor Capital Spending, Wafer Fab Equipment and Capacity, Worldwide, 4Q25 Update, Revenue Basis, Bob Johnson et al., 23 December 2025."

Table of C ontents

Our Technology and Product Offerings

Semiconductor manufacturing is becoming increasingly complex as device scaling, 3D architectures, advanced packaging, and power efficiency requirements place greater demands on yield-critical process steps.

These trends increase the importance of differentiated process equipment capable of operating within tighter tolerances, supporting new materials, and integrating across multiple manufacturing stages.

We develop and deliver a broad portfolio of differentiated semiconductor process equipment that spans front-end wafer fabrication through advanced packaging.

Our product platforms are built around proprietary process technologies and system architectures designed to address increasingly complex device structures, tighter process windows, and rising yield sensitivity at advanced nodes.

Our current business mix is primarily from wet cleaning, plating, and advanced packaging.

We have been investing in the development of new products for several adjacent front-end process steps—including furnace, PECVD, and track—leveraging common design principles, modular platforms, and deep process integration.This multi-product approach enables us to support customers across a larger portion of the manufacturing flow, deepen technical engagement, and is intended to create additional growth opportunities over time.

Wet Cleaning Equipment for Front End Production Processes

Wafer cleaning is a foundational process step in semiconductor manufacturing, directly impacting yield, reliability, and device performance across every major technology node.

As device architectures have evolved toward smaller geometries, higher aspect ratios, and complex 3D structures, cleaning requirements have become increasingly demanding—requiring effective particle and residue removal while minimizing pattern damage and chemical consumption.

Our wet cleaning portfolio is designed to address these challenges through proprietary process technologies, modular architectures, and application-specific configurations that support both advanced and mature nodes.

Our solutions are deployed across multiple front-end process steps and are optimized to balance performance, yield, throughput, cost of ownership, and environmental considerations.

Our wet-cleaning platforms incorporate proprietary SAPS, TEBO, and Tahoe technologies, enabling effective removal of random particles while preserving delicate wafer features, even at increasingly advanced process nodes (the minimum line widths on a chip).

The systems are built on a modular architecture that allows customers to tailor tool configurations to specific process requirements, while leveraging standardized chamber, electrical, chemical delivery, and control modules.

Table of C ontents

This approach supports rapid configuration, efficient qualification, and optimized chemical selection without sacrificing reliability or scalability.

While our tools are primarily designed for 300mm silicon wafer manufacturing, we also offer solutions for 150mm and 200mm wafers, as well as non-standard substrates including compound semiconductors, quartz, sapphire, glass, and plastics.

• Space Alternated Phase Shift, or SAPS, technology for flat and patterned (deep via or deep trench with stronger structure) wafer surfaces.

3 unchanged sentences

TEBO technology has been developed to provide effective, damage-free cleaning for 2D and 3D patterned wafers with fine feature sizes.

We have demonstrated the damage-free cleaning capabilities of TEBO technology on

1 The information contains statistical data and estimates, including forecasts, that are based on information provided by Gartner®, "Forecast:

Semiconductor Capital Spending, Wafer Fab Equipment and Capacity, Worldwide, 4Q24 Update, Bob Johnson et al., 26 December 2024."

patterned wafers for feature nodes as small as 1xnm (16 to 19 nanometers, or nm), and we have shown TEBO technology can be applied in manufacturing processes for patterned chips with 3D architectures having aspect ratios as high as 60‑to‑1.

We have demonstrated the damage-free cleaning capabilities of TEBO technology on patterned wafers for feature nodes as small as 1xnm (16 to 19 nanometers, or nm), and we have shown TEBO technology can be applied in manufacturing processes for patterned chips with 3D architectures having aspect ratios as high as 60‑to‑1.

• Tahoe technology for cost and environmental savings.

Tahoe technology delivers high cleaning performance using significantly less sulfuric acid and hydrogen peroxide than is typically consumed by conventional high-temperature single-wafer cleaning tools.

• Semi-critical cleaning.

Our cleaning portfolio also comprises a suite of semi-critical cleaning products including single wafer back-side cleaning, scrubber, and auto bench.

ECP, Furnace, PECVD, and Track Platforms

Building on our core strengths in wet processing, ACM has expanded into several adjacent front-end process categories, including electrochemical plating (ECP), furnace, PECVD, and track platforms.

Each of these product lines incorporates our differentiated approach to tool design, process control, and modular architecture, allowing us to apply proprietary technologies across multiple steps in the manufacturing flow.

Our ECP portfolio addresses both front-end interconnect formation and back-end advanced packaging applications, while our furnace, PECVD, and track platforms are at earlier stages of customer evaluation and adoption, with meaningful long-term growth potential.

Together, these platforms reflect our strategy to evolve into a broader, multi-product supplier supporting advanced logic, memory, power, and packaging applications.

• ECP technology for advanced metal plating.

2 unchanged sentences

Ultra ECP map offers improved gap-filling performance for ultra-thin seed layer applications, which is critical for advanced nodes at 28nm, 14nm and beyond.

We have also introduced and delivered a range of new tools intended to broaden our revenue opportunity with global semiconductor manufacturers.

Product extensions include the Ultra SFP ap tool for advanced packaging solutions, the Ultra C VI 18-chamber single wafer cleaning tool for advanced memory devices, and the Ultra ECP 3d platform for through-silicon-via, or tsv, application.

New product lines include the Ultra fn Furnace, our first dry processing tool, and a suite of semi-critical cleaning systems which include single wafer back side cleaning, scrubber, and auto bench cleaning tools.

We added two major new product categorie s in 2022 with the launch of the Ultra Pmax™ PECVD tool, which is equipped with a proprietary designed chamber, gas distribution unit and chuck, and is intended to provide better film uniformity, reduced film stress, and improved particle performance, and the introduction of the Ultra Track tool, a 300mm process tool that delivers uniform air downflow, fast robot handling and customizable software to address specific customer requirements, and has multiple features that enhance performance across defectivity, throughput, and cost of ownership.

On November 18, 2021, ACM Shanghai successfully completed its initial public offering of shares of ACM Shanghai in mainland China, which we refer to as the STAR IPO, and its shares began trading on the Shanghai Stock Exchange’s SciTech innovAtion boaRd, known as the STAR Market, which we refer to as the STAR Listing, as described under “Item 7.

Management’s Discussion and Analysis of Financial Condition and Results of Operations.”

Our Technology and Prod uct Offerings

Wet Cleaning Equipment for Front End Production Processes

Chip fabricators can use our single-wafer wet-cleaning tools in numerous steps to improve product yield in the front-end production process, during which individual devices are patterned in a chip prior to being interconnected on a wafer.

Our wet-cleaning equipment has been developed using our proprietary SAPS, TEBO and Tahoe technologies, which allow our tools to remove random defects from a wafer surface effectively, without damaging a wafer or its features, even at increasingly advanced process nodes (the minimum line widths on a chip) of 22nm or less.

We use a modular configuration that enables us to create a wet-cleaning tool meeting the specific requirements of a customer, while using pre-existing designs for chamber, electrical, chemical delivery and other modules.

Our modular approach supports a wide range of customer needs and facilitates the adaptation of our model tools for use with the optimal chemicals selected to meet a customer’s requirements.

Our tools are offered principally for use in manufacturing chips from 300 millimeter, or mm, silicon wafers, but we also offer solutions for 150mm and 200mm wafers and for nonstandard substrates, including compound semiconductor, quartz, sapphire, glass and plastics.

SAPS Technology, Applications and Equipment

SAPS Technology

SAPS technology delivers megasonic energy uniformly to every point on an entire wafer by alternating phases of megasonic waves in the gap between a megasonic transducer and the wafer.

Radicals for removing random defects are generated in dilute solution, and the radical generation is promoted by megasonic energy.

Unlike “stationary” megasonic transducers used in conventional megasonic cleaning methods, SAPS technology moves or tilts a transducer while a wafer rotates, enabling megasonic energy to be delivered uniformly across all points on the wafer, even if the wafer is warped.

The mechanical force of cavitations generated by megasonic energy enhances the mass transfer rate of dislodged random defects and improves particle removal efficiency.

By delivering megasonic energy in a highly uniform manner on a microscopic level, SAPS technology can precisely control the intensity of megasonic energy and can effectively remove random defects of all sizes across the entire wafer in less total cleaning time than conventional megasonic cleaning products, without loss of material or roughing of wafer surfaces.

We have conducted trials demonstrating SAPS technology to be more effective than conventional megasonic and jet spray cleaning technologies as defect sizes shrink from 300nm to 20nm and below.

These trials show that SAPS technology has an even greater relative advantage over conventional jet spray technology for cleaning defects between 50 and 65nm in size, and we expect the relative benefits of SAPS will continue to apply in cleaning even smaller defect sizes.

SAPS Applications

SAPS megasonic cleaning technology can be applied during the chip fabrication process to clean wafer surfaces and interconnects.

It also can be used to clean, and lengthen the lifetime, of recycled test wafers.

Wafer Surfaces.

SAPS technology can enhance removal of random defects following planarization and deposition, which are among the most important, and most repeated, steps in the fabrication process:

Chemical mechanical planarization, or CMP, uses an abrasive chemical slurry following other fabrication processes, such as deposition and etching, in order to achieve a smooth wafer surface in preparation for subsequent processing steps.

SAPS technology can be applied following each CMP process to remove residual random defects deposited or formed during CMP.

• Post Hard Mask Deposition:

As part of the photolithographical patterning process, a mask is applied with each deposition of a material layer to prevent etching of material intended to be retained.

Hard masks have been developed to etch high aspect-ratio features of advanced chips that traditional masks cannot tolerate.

SAPS technology can be applied following each deposition step involving hard masks that use nitride, oxide or carbon-based materials to achieve higher etch selectivity and resolution.

For these purposes, SAPS technology uses environmentally friendly dilute chemicals, reducing chemical consumption.

Chemical types include dilute solutions of chemicals used in RCA cleaning, such as dilute hydrofluoric acid and RCA SC-1 solutions, and, for higher quality wafer cleaning, functional de-ionized water produced by dissolving hydrogen, nitrogen or carbon dioxide in water containing a small amount of chemicals, such as ammonia.

Functional water removes random defects by generating radicals, and megasonic excitation can be used in conjunction with functional water to further increase the generation of radicals.

Functional water has a lower cost and environmental impact than RCA solutions, and using functional water is more efficient in eliminating random defects than using dilute chemicals or de-ionized water alone.

We have shown that SAPS megasonic technology using functional water exhibits high efficiency in removing random defects, especially particles smaller than 65nm, with minimal damage to structures.

Interconnects and Barrier Metals .

Each successive advanced process node has led to finer feature sizes of interconnects such as contacts, which form electrical pathways between a transistor and the first metal layer, and vias, which form electrical pathways between two metal layers.

Advanced nodes have also resulted in higher aspect ratios for interconnect structures, with thinner, redesigned metal barriers being used to prevent diffusion.

SAPS technology can improve the removal of residues and other random defects from interconnects during the chip fabrication process:

• Post Contact/Via Etch:

Wet etching processes are commonly used to create patterns of high-density contacts and vias.

SAPS technology can be applied after each such etching process to remove random defects that could otherwise lead to electrical shorts.

• Pre Barrier-Metal Deposition :

Copper wiring requires metal diffusion barriers at the top of via holes to prevent electrical leakage.

SAPS technology can be applied prior to deposition of barrier metal to remove residual oxidized copper, which otherwise would adhere poorly to the barrier and impair performance.

For these applications, SAPS technology uses environmentally friendly dilute chemicals such as dilute hydrofluoric acid, RCA SC-1 solution, ozonated de-ionized water and functional de-ionized water with dissolved hydrogen.

These chemical solutions take the place of piranha solution, a high-temperature mixture of sulfuric acid and hydrogen peroxide used by conventional wet wafer cleaning processes.

We have shown that SAPS technology exhibits greater efficiency in removing random defects, and lower levels of material loss, than conventional processes, and our chemical solutions are less expensive and more environmentally conscious than piranha solution.

Recycled Test Wafers.

In addition to using silicon wafers for chip production, chip manufacturers routinely process wafers through a limited portion of the front-end fabrication steps in order to evaluate the health, performance and reliability of

Manufacturers also use wafers for non-product purposes such as inline monitoring.

Wafers used for purposes other than manufacturing revenue products are known as test wafers, and it is typical for twenty to thirty percent of the wafers circulating in a fab to be test wafers.

In light of the significant cost of wafers, manufacturers seek to re-use a test wafer for more than one test.

As test wafers are recycled, surface roughness and other defects progressively impair the ability of a wafer to complete tests accurately.

SAPS technology can be applied to reduce random defect levels of a recycled wafer, enabling the test wafer to be reclaimed for use in additional testing processes.

For these purposes, SAPS technology includes improved fan filter units that balances intake and exhaust flows, precise temperature and concentration controls that ensure better handling of concentrated acid processes, and two-chemical recycle capability that reduces chemical consumption.

SAPS Equipment

We offer two principal models of wet wafer cleaning equipment based on our SAPS technology, Ultra C SAPS II and Ultra C SAPS V.

Each of these models is a single-wafer, serial-processing tool that can be configured to customer specifications and, in conjunction with appropriate dilute chemicals, used to remove random defects from wafer surfaces or interconnects and barrier metals as part of the chip front-end fabrication process or for recycling test wafers.

By combining our megasonic and chemical cleaning technologies, we have designed these tools to remove random defects with greater efficacy and efficiency than conventional wafer cleaning processes, with enhanced process flexibility and reduced quantities of chemicals.

Each of our SAPS models was initially built to meet specific requirements of a key customer.

SAPS II (released in 2011).

Highlights of our SAPS II equipment include:

• compact design, with footprint of 2.65m x 4.10m x 2.85m (WxDxH), requiring limited clean room floor space;

• up to 8 chambers, providing throughput of up to 225 wafers per hour;

• double-sided cleaning capability, with up to 5 cleaning chemicals for process flexibility;

• 2-chemical recycling capability for reduced chemical consumption;

• image wafer detection method for lowering wafer breakage rates;

• chemical delivery module for delivery of dilute hydrofluoric acid, RCA SC-1 solution, functional de-ionized water and carbon dioxide to each of the chambers.

SAPS V (released in 2014).

SAPS V includes SAPS II features with the following upgrades:

• compact design, with footprint of 2.55m x 5.1m x 2.85m (WxDxH), requiring limited clean room floor space;

• up to 12 chambers, providing throughput of up to 375 wafers per hour;

• chemical supply system integrated into mainframe;

• inline mixing method replaces tank auto changing, reducing process time;

• improved drying technology using hot isopropyl alcohol and de-ionized water.

TEBO Technology, Applications and Equipment

TEBO Technology

We developed TEBO technology for application in wet wafer cleaning during the fabrication of 2D and 3D wafers with fine feature sizes.

TEBO technology facilitates effective cleaning even with patterned features too small or fragile to be addressed by conventional jet spray and megasonic cleaning technologies.

TEBO technology solves the problems created by transient cavitation in conventional megasonic cleaning processes.

Cavitation is the formation of bubbles in a liquid, and transient cavitation is a process in which a bubble in fluid implodes or collapses.

In conventional megasonic cleaning processes, megasonic energy forms bubbles and then causes those bubbles to implode or collapse, blasting destructive high-pressure, high-temperature micro jets toward the wafer surface.

Our internal testing has confirmed that at any level of megasonic energy capable of removing random defects, the sonic energy and mechanical force generated by transient cavitation are sufficiently strong to damage fragile patterned structures with features less than 70nm.

TEBO technology provides multi-parameter control of cavitation by using a sequence of rapid changes in pressure to force a bubble in liquid to oscillate at controlled sizes, shapes and temperatures, rather than implode or collapse.

As a result, cavitation remains stable during TEBO megasonic cleaning processes, and a chip fabricator can, using TEBO technology, apply the level of megasonic energy needed to remove random defects without incurring the pattern damage created by transient cavitation in conventional megasonic cleaning.

We have demonstrated the damage-free or low-damage cleaning capabilities of TEBO technology on customers’ patterned wafers as small as 1xnm (16nm to 19nm), and we believe TEBO technology will be applicable in even smaller fabrication process nodes.

TEBO technology can be applied in manufacturing processes for conventional 2D chips with fine features and advanced chips with 3D structures, including Fin Field Effect Transistors or FinFET, DRAM, 3D NAND and 3D cross point memory, and we expect it will be applicable to other 3D architectures developed in the future, such as carbon nanotubes and quantum devices.

As a result of the thorough, controlled nature of TEBO processes, cleaning time for TEBO-based solutions may take longer than conventional megasonic cleaning processes.

Conventional processes have proven ineffective, however, for process nodes of 20nm or less, and we believe the increased yield that can be achieved by using TEBO technology for nodes up to 70nm can more than offset the cost of the additional time in utilizing TEBO technology.

TEBO Applications

At process nodes of 28nm and less, chip makers face escalating challenges in eliminating nanometric particles and maintaining the condition of inside pattern surfaces.

In order to maintain chip quality and avoid yield loss, cleaning technologies must control random defects of diminishing killer defect sizes, without roughing or otherwise damaging surfaces of transistors, interconnects or other wafer features.

TEBO technology can be applied in numerous steps throughout the manufacturing process flow for effective, damage-free cleaning:

• Memory Chips:

We estimate that TEBO technology can be applied in as many as 50 steps in the fabrication of a DRAM chip, consisting of up to 10 steps in cleaning ISO structures, 20 steps in cleaning buried gates, and 20 steps in cleaning high aspect-ratio storage nodes and stacked films.

• Logic Chips:

In the fabrication process for a logic chip with a FinFET structure, we estimate that TEBO technology can be used in 15 or more cleaning steps.

For purposes of solving inside pattern surface conditions for memory or logic chips, TEBO technology uses environmentally friendly dilute chemicals such as RCA SC-1 and hydrogen gas doped functional water.

TEBO Equipment

We offer two models of wet wafer cleaning equipment based on our TEBO technology, Ultra C TEBO II and Ultra C TEBO V.

Each of these models is a single-wafer, serial-processing tool that can be configured to customer specifications and, in conjunction with appropriate dilute chemicals, used at numerous manufacturing processing steps for effective, damage-free cleaning of chips at process nodes of 28nm or less.

TEBO equipment solves the problem of pattern damage caused by transient cavitation in conventional jet spray and megasonic cleaning processes, providing better particle

removal efficiency with limited material loss or roughing.

TEBO equipment is being evaluated by a select group of leading memory and logic chip customers.

Each model of TEBO equipment includes:

• an equipment front-end module, or EFEM, which moves wafers from chamber to chamber.

• one or more chamber modules, each equipped with a TEBO megasonic generator system.

• an electrical module to provide power for the tool;

• a chemical delivery module.

Ultra C TEBO II (released in 2016).

Highlights of our Ultra C TEBO II equipment include:

• compact design, with footprint of 2.25m x 2.25m x 2.85m (WxDxH);

• up to 8 chambers with an upgraded transport system and optimized robotic scheduler, providing throughput of up to 300 wafers per hour.

• EFEM module consisting of 4 load ports, transfer robot and 1 process robot;

• focus on dilute chemicals contributes to environmental sustainability and lower cost of ownership.

Ultra C TEBO V (released in 2016).

Highlights of our Ultra C TEBO V equipment include:

• footprint of 2.45m x 5.30m x 2.85m (WxDxH).

• up to 12 chamber modules, providing throughput of up to 300 wafers per hour.

• EFEM module consisting of 4 load ports, 1 transfer robot and 1 process robot:

• chemical delivery module for delivery of isopropyl alcohol, dilute hydrofluoric acid, RCA SC-1 solution, functional de-ionized water and carbon dioxide to each of the chambers.

Tahoe Overview

Our Ultra-C Tahoe wafer cleaning tool can deliver high cleaning performance using significantly less sulfuric acid and hydrogen peroxide than is typically consumed by conventional high-temperature single-wafer cleaning tools.

During normal single-wafer cleaning processes, only a fraction of the acid reacts with the wafer surface, while the majority is wasted as acid spins off the wafer and requires significant cost and effort to be recycled.

Tahoe employs a proprietary hybrid approach in which the sulfuric acid cleaning steps are processed in batch mode, and the final stage cleaning are processed with single-wafer cleaning technologies.

In addition to providing cost savings resulting from vastly reduced sulfuric acid consumption, Ultra-C Tahoe meets the needs of customers who face increased environmental regulations and demand new, more environmentally-friendly tools.

• Ultra fn Furnace.

Our Ultra fn Furnace is our first dry processing tool.

Our Ultra fn vertical furnace features a proprietary quartz-based process chamber capable of operating at temperatures up to 1250°C while maintaining uniformity, a performance level that we believe is not currently achieved by other vertical furnace platforms.

• Ultra Pmax™ PECVD tools.

Our Ultra Pmax™ PECVD products are equipped with a proprietary designed chamber, gas distribution unit and chuck, and is intended to provide better film uniformity, reduced film stress, and improved particle performance.

• Ultra Track.

Our Ultra Track products include a 300mm process tool that delivers uniform air downflow, fast robot handling and configurable software to address specific customer requirements, and has multiple features that enhance performance across defectivity, throughput, and cost of ownership.

Advanced Packaging and other Back-End Processing Tools

We leverage our technology and expertise to provide a range of single-wafer tools for back-end wafer assembly and packaging factories.

We develop, manufacture and sell a wide range of advanced packaging tools, such as coaters, developers, photoresist strippers, scrubbers, wet etchers and copper-plating tools.

We leverage our technology and expertise to provide a range of single-wafer products for back-end wafer assembly and packaging customers.

We develop, manufacture and sell a wide range of advanced packaging equipment, such as coaters, developers, photoresist strippers, scrubbers, wet etchers and copper-plating equipment.

We focus on providing custom-made, differentiated equipment that incorporates customer-requested features at a competitive price.

1 unchanged sentence

Coaters typically provide input and output elevators, shuttle systems and other

Table of C ontents

devices to handle and transport wafers during the coating process.

2 unchanged sentences

The Ultra C Coater is designed to deliver improved throughput and more efficient tool utilization while eliminating particle generation.

Our other advanced packaging tools include:

Our other advanced packaging products include:

Ultra ECP ap, which delivers a uniform metal layer to finished wafers prior to packaging;

5 unchanged sentences

Our Customers

Since 2009 we have delivered more than 1,120 tools to our customers, more than 920 of w hich were repeat orders or acceptances upon contractual performance obligations having been met and thereby generated revenue to us.

The balance of the delivered tools is subject to the customer's acceptance of the tool upon the tool's satisfaction of applicable contractual requirements or subject to the customer's subsequent discretionary commitment to purchase the tool.

To date, substantially all of our sales of equipment for semiconductor-manufacturing have been to customers located in Asia, and we anticipate that a substantial majority of our revenue from these products will continue to come from customers located in this region for the foreseeable future.

To date, substantially all of our sales of equipment for semiconductor-manufacturing have been to customers located in mainland China, and we anticipate that a substantial majority of our revenue from these products will continue to come from customers located in this region for the foreseeable future.

We have begun to add to our efforts to further address customers in North America, Western Europe and Southeast Asia, by expanding our direct sales teams and increasing our global marketing activities.

Our front-end customers have included:

Shanghai Huali Microelectronics Corporation, together with Huahong Semiconductor Ltd., collectively known as The Shanghai Huahong (Group) Company, Ltd., or The Huali Huahong Group, a leading mainland China-based foundry;

Semiconductor Manufacturing International Corporation, or SMIC, a leading mainland China-based foundry;

SK Hynix Inc., a leading Korean memory chip company;

Yangtze Memory Technologies Co., Ltd., or YMTC, a leading mainland China-based memory chip company, together with one of its subsidiaries;

ChangXin Memory Technologies, or CXMT, a leading mainland China-based memory chip company;

Shenzhen Pengxinwei Integrated Circuit Manufacturing Co., Ltd., or PXW, a leading mainland China-based semiconductor foundry company;

and SiEn, a leading mainland China-based power-semiconductor chip company.

Our wafer assembly and packaging customers have included:

Jiangyin Changdian Advanced Packaging Co.

Ltd., a mainland China-based wafer bumping packaging house that is a subsidiary of JCET Group Co., Ltd.;

Nantong Tongfu Microelectronics Co., Ltd., a mainland China-based chip assembly and testing company that is a subsidiary of Nantong Fujitsu Microelectronics Co., Ltd.;

Nepes Co., Ltd., a semiconductor packaging company based in Korea;

and Wafer Works Corporation, a mainland China-based wafer supplier.

In 2024, 52.2% of our revenue was derived from four customers:

The Huali Huahong Group accounted for 14.7% of our revenue;

SMIC accounted for 13.6% of our revenue;

YMTC accounted for 12.0%% of our revenue;

and PXW accounted for 11.9% of our revenue.

In 2023, 45.5% of our revenue was derived from three customers:

SMIC accounted for 16.7% of our revenue;

SiEn accounted for 15.4% of our revenue;

accounted for 13.4% of our revenue.

In 2022, 43.8% of our revenue was derived from three customers:

The Huali Huahong Group;

accounted for 18.2% of our revenue;

SMIC accounted for 15.6% of our revenue, and YMTC accounted for 10.0% of our revenue.

Since 2009 we have delivered m ore than 1,435 tools to our customers, more than 1,255 of which were repeat orders or acceptances upon contractual performance obligations having be en met and thereby generated revenue to us.

Our equipment can generally be configured for use by manufacturers, or customer types, who in turn build a range of different semiconductor types.

Our revenue by customer type was distributed as follows:

Foundry/Logic/Other represented 59%, 71%, and 64% of total revenue in 2025, 2024, and 2023, respectively;

Memory represented 27%, 22%, and 24%;

and Advanced Packaging/Wafer Processing represented 14%, 7%, and 13% for the same periods.

For information on our customer concentration risks with respect to revenue and accounts receivable, see note 2 to the consolidated financial statements included in this report.

Sales and Marketing

4 unchanged sentences

To supplement our direct sales teams, we have contacts with several independent sales representatives in mainland China, Korea and Taiwan.

We select these independent representatives based on their ability to provide effective field sales,

marketing forecast and technical requirement updates for our products.

We select these independent representatives based on their ability to provide effective field sales, marketing forecast and technical requirement updates for our products.

In the case of representatives, our customers place purchase orders with us directly rather than with the representatives.

1 unchanged sentence

Our sales terms and conditions are generally consistent with industry practice but may vary from customer to customer.

We seek to obtain a purchase order two to six months ahead of the customer’s desired delivery date.

Consistent with industry practice, we allow customers to reschedule or cancel orders at a certain cost to them on relatively short notice.

Because of our relatively short delivery period and our practice of permitting rescheduling or cancellation, we believe that backlog is not a reliable indicator of our future revenue.

We seek to obtain a purchase order four to six months ahead of the customer’s desired delivery date.

Consistent with industry practice, customers may delay delivery, adjust, or cancel orders prior to shipment subject to penalties.

Our marketing team focuses on our product strategy and technology road maps, product marketing, new product introduction processes, demand assessment and competitive analysis, customer requirement communication and public relations.

Our marketing team also has the responsibility to conduct environmental scans, study industry trends and arrange our participation at major trade shows.

Table of C ontents

Manufacturing

We conduct a substantial majority of our product development, manufacturing, support and services in mainland China, with additional product development and subsystem production in Korea.

Substantially all of our tools are built to order at our Chuansha manufacturing facilities in the Pudong region of Shanghai.

In the fourth quarter of 2024, we began initial operations at our Lingang development and production center.

The facility, when fully completed, is intended to comprise more than 1,000,000 square feet and incorporate state-of-the-art manufacturing systems and automation technologies to expand our production capacity and support additional research and development activities.

Substantially all of our tools are built to order at our Lingang development and production center.

Properties,” of Part I of this report.

8 unchanged sentences

For this reason, we devote significant financial and personnel resources to research and development.

Our research and development team is comprised of highly skilled engineers and technologists with extensive experience in megasonic and other technologies, cleaning processes and chemistry, mechanical design, and control system design.

For the foreseeable future we are focusing on enhancing our Ultra C SAPS, TEBO, Tahoe, ECP, furnace and other tools and integrating additional capabilities to meet and anticipate requirements from our existing and potential customers.

Our particular areas of focus include development of the following:

• new cleaning steps for Ultra C SAPS cleaners for application in logic chips and for DRAM, and 3D NAND technologies.

• new cleaning steps for Ultra C TEBO cleaners for FinFET in logic chips, gates in DRAM, and deep vias in 3D NAND technologies.

• new cleaning steps for Ultra Tahoe cleaners for application in logic chips and for DRAM and 3D NAND technologies.

• new dry technologies such as supercritical CO2 dry and advanced IPA dry for DRAM, and logic technologies.

• new hardware, including new system platforms, new and additional chamber structures and new chemical blending systems;

• new software to integrate new functionalities to improve tool performance;

• support for the ongoing evaluations and commercialization efforts and product extensions for the newly introduced PECVD and Track product categories.

Our research and development team is comprised of highly skilled engineers and technologists with extensive experience across a range of technologies, cleaning processes and chemistry, mechanical design, and control system design.

Longer term, we are working on new proprietary process capabilities based on our existing tool hardware platforms.

We are also working to integrate our tools with third-party tools in adjacent process areas in the chip manufacturing flow.

Our research and development expense totaled $105.5 million or 13.5% of revenue in 2024, $92.7 million or 16.6% of revenue in 2023, and $62.2 million or 16.0% of revenue in 2022.

We intend to continue to invest in research and development to support and enhance our existing products and to develop future product offerings to build and maintain our technology leadership position.

Intellectual Property

7 unchanged sentences

Our patent strategy is designed to provide a balance between the need for coverage in our strategic markets and the need to maintain costs at a reasonable level.

As o f December 31, 2024, we have been issued more than 537 patents in the United States, mainland China, Japan, Korea, Singapore and Taiwan, including 76 issued patents, and 32 patents pending, in the United States.

As of December 31, 2025, we have been issued more than 594 patents in the United States, mainland China, Japan, Korea, Singapore and Taiwan, including 82 issued patents, and 33 patents pending, in the United States.

These patents carry expiration dates from 2027 through 2045.

8 unchanged sentences

We may enter into licensing or cross-licensing arrangements with other companies in the future.

Table of C ontents

We cannot assure you that any patents will issue from any of our pending applications.

13 unchanged sentences

We compete with semiconductor equipment companies located around the world, and we may also face competition from new and emerging companies, including new competitors from mainland China.

We consider our principal competitors to be those companies that provide wafer cleaning and electrical plating products to the market, including Lam Research Corporation, NAURA Technology Group Co., Ltd., Mujin Electronics Co., Ltd., SCREEN SPE USA, LLC (a subsidiary of SCREEN Holdings Co., Ltd.), SEMES Co.

We consider our principal competitors to be those companies that provide wafer cleaning, electrical plating and furnace products to the global market, including Lam Research Corporation, NAURA Technology Group Co., Ltd., SCREEN Holdings Co., Ltd., SEMES Co.

Ltd., Tokyo Electron Ltd.

and Kokusai Semiconductor Equipment Corporation.

Key competitors for our newly-introduced PECVD and Track products include Lam Research Corporation, Applied Materials, Inc., KINGSEMI Co., Ltd.

and Suzhou Jingtuo Semiconductor Technology Co., Ltd.

Principal competitors for our PECVD and Track products also include Lam Research Corporation, Applied Materials, Inc., and Suzhou Jingtuo Semiconductor Technology Co., Ltd .

We also face additional competitors based in mainland China across multiple product lines due in part to the recent entrants of local equipment suppliers.

Compared to our company, our current and potential competitors may have:

13 unchanged sentences

In addition, semiconductor manufacturers must make a substantial investment to qualify and integrate new equipment into semiconductor production lines.

Once a semiconductor manufacturer has selected a particular supplier’s equipment and qualified it for production, the manufacturer generally maintains that selection for that specific production application and technology node as long as the supplier’s products demonstrate performance to specification in the installed base.

Table of C ontents

technology node as long as the supplier’s products demonstrate performance to specification in the installed base.

Accordingly, we may experience difficulty in selling to a given manufacturer if that manufacturer has qualified a competitor’s equipment.

28 unchanged sentences

We have designed some of our tools to require significantly reduced levels of environmentally harmful chemicals, which helps customers face increased environmental laws and regulations.

SAPS and TEBO technologies use environmentally friendly dilute chemicals, such as dilute hydrofluoric acid, RCA SC-1 solution, ozonated de-ionized water and functional de-ionized water with dissolved hydrogen.

SAPS and TEBO technologies use environmentally

Table of C ontents

friendly dilute chemicals, such as dilute hydrofluoric acid, RCA SC-1 solution, ozonated de-ionized water and functional de-ionized water with dissolved hydrogen.

In interconnect and barrier metals applications based on SAPS technology, for example, these chemical solutions take the place of chemicals such as piranha solution, a high-temperature mixture of sulfuric acid and hydrogen peroxide used by conventional wet wafer cleaning processes.

12 unchanged sentences

Compared sentence by sentence after normalising whitespace, quotation marks, case and digits, so re-formatting and restated figures do not read as changed language. Wording changes appear as one removal and one addition. The current filing and the prior one are authoritative.

What changed 10-K

Item 1. Business