What changed in this filing

/stocks — the workspaceLOADING

Item 1. Business

2024-02-28 compared with 2023-03-02 · 201 added, 411 removed, 166 unchanged (79% of the section changed)

We supply advanced, innovative capital equipment developed for the global semiconductor industry.

Fabricators of advanced integrated circuits, or chips, can use our wet-cleaning and other

front-end processing tools in numerous steps to improve product yield, even at increasingly advanced process nodes.

We have designed these tools for use in fabricating foundry, logic and memory chips, including dynamic random-access memory, or

DRAM, and 3D NAND-flash memory chips.

Fabricators of advanced integrated circuits, or chips, can use our wet-cleaning and other front-end processing tools in numerous steps to improve product yield, even at increasingly advanced process nodes.

We have designed these tools for use in fabricating foundry, logic and memory chips, including dynamic random-access memory, or DRAM, and 3D NAND-flash memory chips.

We also develop, manufacture and sell a range of advanced packaging tools to wafer assembly and packaging customers.

Revenue from wet cleaning and other front-end processing tools totaled $308.5 million, or 79.3% of total revenue in 2022, $202.3 million, or 77.9% of total revenue in 2021, and $136.3 million, or

87.0% of total revenue in 2020.

Selling prices for our wet-cleaning and other front-end processing tools range from $0.7 million to more than $5 million.

Our customers for wet-cleaning and other front-end processing tools have included Shanghai

Huali Microelectronics Corporation, together with Huahong Semiconductor Ltd., collectively known as The Shanghai Huahong (Group) Company, Ltd., or The Huali Huahong Group, Semiconductor Manufacturing International Corporation, or SMIC, Shanghai

SK Hynix Inc., Yangtze Memory Technologies Co., Ltd., or YMTC, and ChangXin Memory Technologies.

Revenue from advanced packaging, other processing tools, services and spares totaled $80.3 million, or 20.7% of total revenue in 2022, $57.5 million, or 22.1% of total revenue in 2021, and $20.4

million, or 13.0% of total revenue in 2020.

Selling prices for these tools range from $0.5 million to more than $4 million.

Our customers for advanced packaging, and other processing tools have included Jiangyin Changdian Advanced Packaging

Ltd., a leading PRC-based wafer bumping packaging house that is a subsidiary of JCET Group Co., Ltd.;

Nantong Tongfu Microelectronics Co., Ltd., a PRC-based chip assembly and testing company that is a subsidiary of Nantong Fujitsu

Microelectronics Co., Ltd.;

Nepes Co., Ltd., a semiconductor packaging company based in South Korea which acquired the operations of Deca Technologies’ Philippines manufacturing facility in 2020;

and Wafer Works Corporation, a leading

PRC-based wafer supplier.

We estimate, based on third-party reports and on customer and other information, that our current product portfolio addresses approximately $16 billion of the 2022 global wafer fab equipment, or

By product line, we estimate an approximately $4.6 billion market opportunity is addressed by our wafer cleaning equipment, $4.3 billion by our Plasma-Enhanced Chemical Vapor Deposition, or PECVD, equipment, $3.2 billion by our

furnace equipment, $2.6 billion by our Track equipment, $800 million by our electro-chemical plating, or ECP, equipment, and more than $800 million by our stress-free polishing, advanced packaging, wafer processing, and other processing

Based on Gartner’s estimates, the total available global market for these equipment segments increased by 7.6% from $20.1 billion in 2021, to $21.6 billion in 2022, and is expected to decrease by

19.6% to $17.4 billion in 2023.

These equipment segments are a subset of the total worldwide semiconductor WFE market, which Gartner estimates increased by 8.9% from $92.4 billion in 2021 to $100.5 billion in 2022, and estimates will decrease

by 19.0% to $81.5 billion in 2023.

We have focused our selling efforts on establishing a referenceable base of leading foundry, logic and memory chip makers, whose use of our products can influence

decisions by other manufacturers.

Revenue from single wafer cleaning, Tahoe and semi-critical cleaning equipment totaled $403.9 million, or 72.4% of total revenue in 2023, $272.9 million, or 70.2% of total revenue in 2022, and $189.2 million, or 72.8% of total revenue in 2021.

Revenue from ECP (front-end packaging), furnace and other technologies totaled $103.4 million, or 18.5% of total revenue, in 2023, $77.5 million, or 19.9% of total revenue in 2022, and $33.2 million, or 12.8% of total revenue in 2021.

Revenue from advanced packaging (excluding ECP), services and spares totaled $50.5 million, or 9.1% of total revenue, in 2023, $38.4 million, or 9.9% of total revenue in 2022, and $37.3 million, or 14.4% of total revenue in 2021.

Selling prices for our tools generally range from $0.5 million to more than $5 million.

We estimate, based on third-party reports and on customer and other information, that our current product portfolio addresses approximately $16 billion of the 2023 global wafer fab equipment, or WFE, market.

By product line, we estimate an approximately $5.2 billion market opportunity is addressed by our wafer cleaning equipment, $4.3 billion by our Plasma-Enhanced Chemical Vapor Deposition, or PECVD, equipment, $2.2 billion by our furnace equipment, $2.5 billion by our Track equipment, $800 million by our electro-chemical plating, or ECP, equipment, and more than $900 million by our stress-free polishing, advanced packaging, wafer processing, and other processing equipment.

Based on Gartner’s estimates, the total available global market for these equipment segments decreased by 11.4% from $21.2 billion in 2022, to $18.7 billion in 2023, and is expected to decrease by 2.8% to $18.2 billion in 2024.

These equipment segments are a subset of the total worldwide semiconductor WFE market, which Gartner estimates decreased by 7.7% from $100.6 billion in 2022 to $92.9 billion in 2023, and estimates will decrease by 1.7% to $91.3 billion in 2024.

We have focused our selling efforts on establishing a referenceable base of leading foundry, logic and memory chip makers, whose use of our products can influence decisions by other manufacturers.

We believe this customer base has helped us penetrate the mature chip manufacturing markets and build credibility with additional industry leaders.

We have used a “demo-to-sales” process to place evaluation

equipment, or “first tools,” with a number of selected customers.

To date, a substantial majority of our sales of single-wafer wet-cleaning equipment for front-end manufacturing have been to customers located in Asia, and we anticipate that a substantial

majority of our revenue from these products will continue to come from customers located in this region for the foreseeable future.

We have begun to add to our efforts to further address customers in North America, Western Europe and Southeast Asia by expanding our direct sales and services teams and increasing our global

marketing activities.

operation includes sales, marketing and services personnel to expand and support major new customer initiatives for the products of ACM Shanghai to additional regions beyond mainland China.

As of December 31,

2022, we have delivered one tool for evaluation to a U.S.

lab of a global semiconductor capital equipment vendor, and two tools to the U.S.

facility of a major U.S.

semiconductor manufacturer.

Both of these evaluations are supported by our

services team.

We have used a “demo-to-sales” process to place evaluation equipment, or “first tools,” with a number of selected customers.

To date, a substantial majority of our sales of single-wafer wet-cleaning equipment for front-end manufacturing have been to customers located in Asia, and we anticipate that a substantial majority of our revenue from these products will continue to come from customers located in this region for the foreseeable future.

Our operation includes sales, marketing and services personnel in North America, Western Europe and Southeast Asia to expand and support major new customer initiatives for the products of ACM Shanghai to additional regions beyond mainland China.

We are focused on building a strategic portfolio of intellectual property to support and protect our key innovations.

1 unchanged sentence

• Space Alternated Phase Shift, or SAPS, technology for flat and patterned (deep via or deep trench with stronger structure) wafer surfaces.

SAPS technology employs

alternating phases of megasonic waves to deliver megasonic energy in a highly uniform manner on a microscopic level.

We have shown SAPS technology to be more effective than conventional megasonic and jet spray technologies in

removing random defects across an entire wafer, with increasing relative effectiveness at more advanced production nodes.

SAPS technology employs alternating phases of megasonic waves to deliver megasonic energy in a highly uniform manner on a microscopic level.

We have shown SAPS technology to be more effective than conventional megasonic and jet spray technologies in removing random defects across an entire wafer, with increasing relative effectiveness at more advanced production nodes.

• Timely Energized Bubble Oscillation, or TEBO, technology for patterned wafer surfaces at advanced process nodes .

TEBO technology has been developed to provide

effective, damage-free cleaning for 2D and 3D patterned wafers with fine feature sizes.

We have demonstrated the damage-free cleaning capabilities of TEBO technology on patterned wafers for feature nodes as small as 1xnm (16 to 19

nanometers, or nm), and we have shown TEBO technology can be applied in manufacturing processes for patterned chips with 3D architectures having aspect ratios as high as 60‑to‑1.

TEBO technology has been developed to provide effective, damage-free cleaning for 2D and 3D patterned wafers with fine feature sizes.

We have demonstrated the damage-free cleaning capabilities of TEBO technology on patterned wafers for feature nodes as small as 1xnm (16 to 19 nanometers, or nm), and we have shown TEBO technology can be applied in manufacturing processes for patterned chips with 3D architectures having aspect ratios as high as 60‑to‑1.

• Tahoe technology for cost and environmental savings.

Tahoe technology delivers high cleaning performance using significantly less sulfuric acid and hydrogen peroxide

than is typically consumed by conventional high-temperature single-wafer cleaning tools.

Tahoe technology delivers high cleaning performance using significantly less sulfuric acid and hydrogen peroxide than is typically consumed by conventional high-temperature single-wafer cleaning tools.

• ECP technology for advanced metal plating.

Our Ultra ECP ap, or Advanced Packaging, technology was developed for back-end assembly processes to deliver a more uniform

metal layer at the notch area of wafers prior to packaging.

Our Ultra ECP map, or Multi-Anode Partial Plating, technology was developed for front-end wafer fabrication processes to deliver advanced electrochemical copper plating for

copper interconnect applications.

Our Ultra ECP ap, or Advanced Packaging, technology was developed for back-end assembly processes to deliver a more uniform metal layer at the notch area of wafers prior to packaging.

Our Ultra ECP map, or Multi-Anode Partial Plating, technology was developed for front-end wafer fabrication processes to deliver advanced electrochemical copper plating for copper interconnect applications.

Ultra ECP map offers improved gap-filling performance for ultra-thin seed layer applications, which is critical for advanced nodes at 28nm, 14nm and beyond.

In 2020, 2021 and 2022 we introduced and delivered a range of new tools intended to broaden our revenue opportunity with global semiconductor manufacturers.

Product extensions include the Ultra

SFP ap tool for advanced packaging solutions, the Ultra C VI 18-chamber single wafer cleaning tool for advanced memory devices, and the Ultra ECP 3d platform for through-silicon-via, or tsv, application.

New product lines include the Ultra fn

Furnace, our first dry processing tool, and a suite of semi-critical cleaning systems which include single wafer back side cleaning, scrubber, and auto bench cleaning tools.

We added two major new product categories in 2022 with the launch of the Ultra Pmax™ PECVD tool, which is equipped with a proprietary designed chamber, gas distribution unit and chuck, and is

intended to provide better film uniformity, reduced film stress, and improved particle performance, and the introduction of the Ultra Track tool, a 300mm process tool that delivers uniform air downflow, fast robot handling and customizable

software to address specific customer requirements, and has multiple features that enhance performance across defectivity, throughput, and cost of ownership.

We have been issued more than 448 patents in the United States, the People’s Republic of China, or PRC, Japan, Singapore, South Korea and Taiwan.

We conduct a substantial majority of our product development, manufacturing, support and services in the PRC, with additional product development and subsystem production in South Korea.

Substantially all of our integrated tools are built to order at our manufacturing facilities in the Pudong region of Shanghai, which now encompass a total of 236,000 square feet of floor space for production capacity, with leased buildings at

our Chuansha campus.

We have also introduced and delivered a range of new tools intended to broaden our revenue opportunity with global semiconductor manufacturers.

Product extensions include the Ultra SFP ap tool for advanced packaging solutions, the Ultra C VI 18-chamber single wafer cleaning tool for advanced memory devices, and the Ultra ECP 3d platform for through-silicon-via, or tsv, application.

New product lines include the Ultra fn Furnace, our first dry processing tool, and a suite of semi-critical cleaning systems which include single wafer back side cleaning, scrubber, and auto bench cleaning tools.

We added two major new product categorie s in 2022 with the launch of the Ultra Pmax™ PECVD tool, which is equipped with a proprietary designed chamber, gas distribution unit and chuck, and is intended to provide better film uniformity, reduced film stress, and improved particle performance, and the introduction of the Ultra Track tool, a 300mm process tool that delivers uniform air downflow, fast robot handling and customizable software to address specific customer requirements, and has multiple features that enhance performance across defectivity, throughput, and cost of ownership.

We have been issued more than 498 patents in the United States, the People’s Republic of China, or mainland China, Japan, Singapore, Korea and Taiwan.

We conduct a substantial majority of our product development, manufacturing, support and services in mainland China, with additional product development and subsystem production in Korea.

Substantially all of our integrated tools are built to order at our manufacturing facilities in the Pudong region of Shanghai, which now encompass a total o f 236,000 square feet of floor space for production capacity, with leased buildings at our Chuansha campus.

In May 2020 ACM Shanghai, through its wholly owned subsidiary Shengwei Research (Shanghai), Inc., or ACM Shengwei, entered into an agreement for a land use right in the Lingang region of Shanghai.

In 2020 ACM Shengwei began

a multi-year construction project for a new 1,000,000 square foot development and production center that will incorporate state-of-the-art manufacturing systems and automation technologies and will provide floor space to support significantly

increased production capacity and related research and development, or R&D, activities.

We expect to complete construction of the first Lingang manufacturing building and commence initial production in the second half of 2023 timeframe.

Our experience has shown that chip manufacturers in the PRC and throughout Asia demand equipment that meets their specific technical requirements and generally prefer to build relationships with

local suppliers.

We will continue to seek to leverage our local presence in the PRC and South Korea through our subsidiaries to address the growing market for semiconductor manufacturing equipment in the region by working closely with regional

chip manufacturers to understand their specific requirements, encourage them to adopt our technologies, and enable us to design innovative products and solutions to address their needs.

On November 18, 2021, ACM Shanghai successfully completed its initial public offering of shares of ACM Shanghai in the PRC, which we refer to as the STAR IPO, and its shares began trading on the

Shanghai Stock Exchange’s Sci-Tech innovAtion boaRd, known as the STAR Market, which we refer to as the STAR Listing, as described under “Item 7.

In 2020 ACM Shengwei began a multi-year construction project for a new 1,000,000 square foot development and production center that will incorporate state-of-the-art manufacturing systems and automation technologies and will provide floor space to support significantly increased production capacity and related research and development, or R&D, activities.

We expect to commence initial operations and production activities at our Lingang facilities in the first half of 2024 timeframe.

Our experience has shown that chip manufacturers in mainland China and throughout Asia demand equipment that meets their specific technical requirements and generally prefer to build relationships with local suppliers.

We will continue to seek to leverage our local presence in mainland China and Korea through our subsidiaries to address the growing market for semiconductor manufacturing equipment in the region by working closely with regional chip manufacturers to understand their specific requirements, encourage them to adopt our technologies, and enable us to design innovative products and solutions to address their needs.

On November 18, 2021, ACM Shanghai successfully completed its initial public offering of shares of ACM Shanghai in mainland China, which we refer to as the STAR IPO, and its shares began trading on the Shanghai Stock Exchange’s SciTech innovAtion boaRd, known as the STAR Market, which we refer to as the STAR Listing, as described under “Item 7.

Management’s Discussion and Analysis of Financial Condition and Results of Operations.”

Our Technology and Product Offerings

Our Technology and Prod uct Offerings

Wet Cleaning Equipment for Front End Production Processes

Chip fabricators can use our single-wafer wet-cleaning tools in numerous steps to improve product yield in the front-end production process, during which individual devices are patterned in a chip

prior to being interconnected on a wafer.

wafer or its features, even at increasingly advanced process nodes (the minimum line widths on a chip) of 22nm or less.

We use a modular configuration that enables us to create a wet-cleaning tool meeting the specific requirements of a

customer, while using pre-existing designs for chamber, electrical, chemical delivery and other modules.

Our modular approach supports a wide range of customer needs and facilitates the adaptation of our model tools for use with the optimal

chemicals selected to meet a customer’s requirements.

Our tools are offered principally for use in manufacturing chips from 300 millimeter, or mm, silicon wafers, but we also offer solutions for 150mm and 200mm wafers and for nonstandard

substrates, including compound semiconductor, quartz, sapphire, glass and plastics.

Chip fabricators can use our single-wafer wet-cleaning tools in numerous steps to improve product yield in the front-end production process, during which individual devices are patterned in a chip prior to being interconnected on a wafer.

Our wet-cleaning equipment has been developed using our proprietary SAPS, TEBO and Tahoe technologies, which allow our tools to remove random defects from a wafer surface effectively, without damaging a wafer or its features, even at increasingly advanced process nodes (the minimum line widths on a chip) of 22nm or less.

We use a modular configuration that enables us to create a wet-cleaning tool meeting the specific requirements of a customer, while using pre-existing designs for chamber, electrical, chemical delivery and other modules.

Our modular approach supports a wide range of

customer needs and facilitates the adaptation of our model tools for use with the optimal chemicals selected to meet a customer’s requirements.

Our tools are offered principally for use in manufacturing chips from 300 millimeter, or mm, silicon wafers, but we also offer solutions for 150mm and 200mm wafers and for nonstandard substrates, including compound semiconductor, quartz, sapphire, glass and plastics.

SAPS Technology, Applications and Equipment

1 unchanged sentence

SAPS technology delivers megasonic energy uniformly to every point on an entire wafer by alternating phases of megasonic waves in the gap between a megasonic transducer and the wafer.

removing random defects are generated in dilute solution, and the radical generation is promoted by megasonic energy.

Unlike “stationary” megasonic transducers used in conventional megasonic cleaning methods, SAPS technology moves or tilts a

transducer while a wafer rotates, enabling megasonic energy to be delivered uniformly across all points on the wafer, even if the wafer is warped.

The mechanical force of cavitations generated by megasonic energy enhances the mass transfer rate

of dislodged random defects and improves particle removal efficiency.

By delivering megasonic energy in a highly uniform manner on a microscopic level, SAPS technology can precisely control the intensity of megasonic energy and can effectively remove random defects

of all sizes across the entire wafer in less total cleaning time than conventional megasonic cleaning products, without loss of material or roughing of wafer surfaces.

We have conducted trials demonstrating SAPS technology to be more effective

than conventional megasonic and jet spray cleaning technologies as defect sizes shrink from 300nm to 20nm and below.

These trials show that SAPS technology has an even greater relative advantage over conventional jet spray technology for

cleaning defects between 50 and 65nm in size, and we expect the relative benefits of SAPS will continue to apply in cleaning even smaller defect sizes.

Radicals for removing random defects are generated in dilute solution, and the radical generation is promoted by megasonic energy.

Unlike “stationary” megasonic transducers used in conventional megasonic cleaning methods, SAPS technology moves or tilts a transducer while a wafer rotates, enabling megasonic energy to be delivered uniformly across all points on the wafer, even if the wafer is warped.

The mechanical force of cavitations generated by megasonic energy enhances the mass transfer rate of dislodged random defects and improves particle removal efficiency.

By delivering megasonic energy in a highly uniform manner on a microscopic level, SAPS technology can precisely control the intensity of megasonic energy and can effectively remove random defects of all sizes across the entire wafer in less total cleaning time than conventional megasonic cleaning products, without loss of material or roughing of wafer surfaces.

We have conducted trials demonstrating SAPS technology to be more effective than conventional megasonic and jet spray cleaning technologies as defect sizes shrink from 300nm to 20nm and below.

These trials show that SAPS technology has an even greater relative advantage over conventional jet spray technology for cleaning defects between 50 and 65nm in size, and we expect the relative benefits of SAPS will continue to apply in cleaning even smaller defect sizes.

SAPS Applications

SAPS megasonic cleaning technology can be applied during the chip fabrication process to clean wafer surfaces and interconnects.

It also can be used to clean, and lengthen the lifetime, of

recycled test wafers.

It also can be used to clean, and lengthen the lifetime, of recycled test wafers.

Wafer Surfaces.

SAPS technology can enhance removal of random defects following planarization and deposition, which are among the most important, and most

repeated, steps in the fabrication process:

Chemical mechanical planarization, or CMP, uses an abrasive chemical slurry following other fabrication processes, such as deposition and etching, in order to

achieve a smooth wafer surface in preparation for subsequent processing steps.

SAPS technology can enhance removal of random defects following planarization and deposition, which are among the most important, and most repeated, steps in the fabrication process:

Chemical mechanical planarization, or CMP, uses an abrasive chemical slurry following other fabrication processes, such as deposition and etching, in order to achieve a smooth wafer surface in preparation for subsequent processing steps.

SAPS technology can be applied following each CMP process to remove residual random defects deposited or formed during CMP.

• Post Hard Mask Deposition:

As part of the photolithographical patterning process, a mask is applied with each deposition of a material layer to prevent etching of

material intended to be retained.

As part of the photolithographical patterning process, a mask is applied with each deposition of a material layer to prevent etching of material intended to be retained.

Hard masks have been developed to etch high aspect-ratio features of advanced chips that traditional masks cannot tolerate.

SAPS technology can be applied following each deposition step involving hard

masks that use nitride, oxide or carbon-based materials to achieve higher etch selectivity and resolution.

SAPS technology can be applied following each deposition step involving hard masks that use nitride, oxide or carbon-based materials to achieve higher etch selectivity and resolution.

For these purposes, SAPS technology uses environmentally friendly dilute chemicals, reducing chemical consumption.

Chemical types include dilute solutions of chemicals used in RCA cleaning, such

as dilute hydrofluoric acid and RCA SC-1 solutions, and, for higher quality wafer cleaning, functional de-ionized water produced by dissolving hydrogen, nitrogen or carbon dioxide in water containing a small amount of chemicals, such as

Chemical types include dilute solutions of chemicals used in RCA cleaning, such as dilute hydrofluoric acid and RCA SC-1 solutions, and, for higher quality wafer cleaning, functional de-ionized water produced by dissolving hydrogen, nitrogen or carbon dioxide in water containing a small amount of chemicals, such as ammonia.

Functional water removes random defects by generating radicals, and megasonic excitation can be used in conjunction with functional water to further increase the generation of radicals.

Functional water has a lower cost and

environmental impact than RCA solutions, and using functional water is more efficient in eliminating random defects than using dilute chemicals or de-ionized water alone.

We have shown that SAPS megasonic technology using functional water

exhibits high efficiency in removing random defects, especially particles smaller than 65nm, with minimal damage to structures.

Functional water has a lower cost and environmental impact than RCA solutions, and using functional water is more efficient in eliminating random defects than using dilute chemicals or de-ionized water alone.

We have shown that SAPS megasonic technology using functional water exhibits high efficiency in removing random defects, especially particles smaller than 65nm, with minimal damage to structures.

Interconnects and Barrier Metals .

Each successive advanced process node has led to finer feature sizes of interconnects such as contacts, which form

electrical pathways between a transistor and the first metal layer, and vias, which form electrical pathways between two metal layers.

Advanced nodes have also resulted in higher aspect ratios for interconnect structures, with thinner,

redesigned metal barriers being used to prevent diffusion.

Each successive advanced process node has led to finer feature sizes of interconnects such as contacts, which form electrical pathways between a transistor and the first metal layer, and vias, which form electrical pathways between two metal layers.

Advanced nodes have also resulted in higher aspect ratios for interconnect

structures, with thinner, redesigned metal barriers being used to prevent diffusion.

SAPS technology can improve the removal of residues and other random defects from interconnects during the chip fabrication process:

1 unchanged sentence

Wet etching processes are commonly used to create patterns of high-density contacts and vias.

SAPS technology can be applied after each such

etching process to remove random defects that could otherwise lead to electrical shorts.

SAPS technology can be applied after each such etching process to remove random defects that could otherwise lead to electrical shorts.

• Pre Barrier-Metal Deposition :

Copper wiring requires metal diffusion barriers at the top of via holes to prevent electrical leakage.

SAPS technology can be applied

prior to deposition of barrier metal to remove residual oxidized copper, which otherwise would adhere poorly to the barrier and impair performance.

For these applications, SAPS technology uses environmentally friendly dilute chemicals such as dilute hydrofluoric acid, RCA SC-1 solution, ozonated de-ionized water and functional de-ionized

water with dissolved hydrogen.

SAPS technology can be applied prior to deposition of barrier metal to remove residual oxidized copper, which otherwise would adhere poorly to the barrier and impair performance.

For these applications, SAPS technology uses environmentally friendly dilute chemicals such as dilute hydrofluoric acid, RCA SC-1 solution, ozonated de-ionized water and functional de-ionized water with dissolved hydrogen.

These chemical solutions take the place of piranha solution, a high-temperature mixture of sulfuric acid and hydrogen peroxide used by conventional wet wafer cleaning processes.

We have shown that SAPS technology

exhibits greater efficiency in removing random defects, and lower levels of material loss, than conventional processes, and our chemical solutions are less expensive and more environmentally conscious than piranha solution.

We have shown that SAPS technology exhibits greater efficiency in removing random defects, and lower levels of material loss, than conventional processes, and our chemical solutions are less expensive and more environmentally conscious than piranha solution.

Recycled Test Wafers.

In addition to using silicon wafers for chip production, chip manufacturers routinely process wafers through a limited portion of the

front-end fabrication steps in order to evaluate the health, performance and reliability of those steps.

In addition to using silicon wafers for chip production, chip manufacturers routinely process wafers through a limited portion of the front-end fabrication steps in order to evaluate the health, performance and reliability of those steps.

Manufacturers also use wafers for non-product purposes such as inline monitoring.

Wafers used for purposes other than manufacturing revenue

products are known as test wafers, and it is typical for twenty to thirty percent of the wafers circulating in a fab to be test wafers.

In light of the significant cost of wafers, manufacturers seek to re-use a test wafer for more than one

Wafers used for purposes other than manufacturing revenue products are known as test wafers, and it is typical for twenty to thirty percent of the wafers circulating in a fab to be test wafers.

In light of the significant cost of wafers, manufacturers seek to re-use a test wafer for more than one test.

As test wafers are recycled, surface roughness and other defects progressively impair the ability of a wafer to complete tests accurately.

SAPS technology can be applied to reduce random defect levels of a recycled wafer, enabling the

test wafer to be reclaimed for use in additional testing processes.

For these purposes, SAPS technology includes improved fan filter units that balances intake and exhaust flows, precise temperature and concentration controls that ensure better

handling of concentrated acid processes, and two-chemical recycle capability that reduces chemical consumption.

SAPS technology can be applied to reduce random defect levels of a recycled wafer, enabling the test wafer to be reclaimed for use in additional testing processes.

For these purposes, SAPS technology includes improved fan filter units that balances intake and exhaust flows, precise temperature and concentration controls that ensure better handling of concentrated acid processes, and two-chemical recycle capability that reduces chemical consumption.

SAPS Equipment

We offer two principal models of wet wafer cleaning equipment based on our SAPS technology, Ultra C SAPS II and Ultra C SAPS V.

Each of these models is a single-wafer, serial-processing tool that

can be configured to customer specifications and, in conjunction with appropriate dilute chemicals, used to remove random defects from wafer surfaces or interconnects and barrier metals as part of the chip front-end fabrication process or for

recycling test wafers.

By combining our megasonic and chemical cleaning technologies, we have designed these tools to remove random defects with greater efficacy and efficiency than conventional wafer cleaning processes, with enhanced process

flexibility and reduced quantities of chemicals.

Each of these models is a single-wafer, serial-processing tool that can be configured to customer specifications and, in conjunction with appropriate dilute chemicals, used to remove random defects from wafer surfaces or interconnects and barrier metals as part of the chip front-end fabrication process or for recycling test wafers.

Each of our SAPS models was initially built to meet specific requirements of a key customer.

6 unchanged sentences

• image wafer detection method for lowering wafer breakage rates;

● chemical delivery module for delivery of dilute hydrofluoric acid, RCA SC-1 solution, functional de-ionized water and carbon dioxide to each of

the chambers.

• chemical delivery module for delivery of dilute hydrofluoric acid, RCA SC-1 solution, functional de-ionized water and carbon dioxide to each of the chambers.

SAPS V (released in 2014).

8 unchanged sentences

We developed TEBO technology for application in wet wafer cleaning during the fabrication of 2D and 3D wafers with fine feature sizes.

TEBO technology facilitates effective cleaning even with

patterned features too small or fragile to be addressed by conventional jet spray and megasonic cleaning technologies.

TEBO technology facilitates effective cleaning even with patterned features too small or fragile to be addressed by conventional jet spray and megasonic cleaning technologies.

TEBO technology solves the problems created by transient cavitation in conventional megasonic cleaning processes.

Cavitation is the formation of bubbles in a liquid, and transient cavitation is a

process in which a bubble in fluid implodes or collapses.

In conventional megasonic cleaning processes, megasonic energy forms bubbles and then causes those bubbles to implode or collapse, blasting destructive high-pressure, high-temperature

micro jets toward the wafer surface.

Our internal testing has confirmed that at any level of megasonic energy capable of removing random defects, the sonic energy and mechanical force generated by transient cavitation are sufficiently strong to

damage fragile patterned structures with features less than 70nm.

TEBO technology provides multi-parameter control of cavitation by using a sequence of rapid changes in pressure to force a bubble in liquid to oscillate at controlled sizes, shapes and

temperatures, rather than implode or collapse.

As a result, cavitation remains stable during TEBO megasonic cleaning processes, and a chip fabricator can, using TEBO technology, apply the level of megasonic energy needed to remove random

defects without incurring the pattern damage created by transient cavitation in conventional megasonic cleaning.

We have demonstrated the damage-free or low-damage cleaning capabilities of TEBO technology on customers’ patterned wafers as small as 1xnm (16nm to 19nm), and we believe TEBO technology will be

applicable in even smaller fabrication process nodes.

TEBO technology can be applied in manufacturing processes for conventional 2D chips with fine features and advanced chips with 3D structures, including Fin Field Effect Transistors or

FinFET, DRAM, 3D NAND and 3D cross point memory, and we expect it will be applicable to other 3D architectures developed in the future, such as carbon nanotubes and quantum devices.

As a result of the thorough, controlled nature of TEBO

processes, cleaning time for TEBO-based solutions may take longer than conventional megasonic cleaning processes.

Conventional processes have proven ineffective, however, for process nodes of 20nm or less, and we believe the increased yield

that can be achieved by using TEBO technology for nodes up to 70nm can more than offset the cost of the additional time in utilizing TEBO technology.

Cavitation is the formation of bubbles in a liquid, and transient cavitation is a process in which a bubble in fluid implodes or collapses.

In conventional megasonic cleaning processes, megasonic energy forms bubbles and then causes those bubbles to implode or collapse, blasting destructive high-pressure, high-temperature micro jets toward the wafer surface.

TEBO technology provides multi-parameter control of cavitation by using a sequence of rapid changes in pressure to force a bubble in liquid to oscillate at controlled sizes, shapes and temperatures, rather than implode or collapse.

As a result, cavitation remains stable during TEBO megasonic cleaning processes, and a chip fabricator can, using TEBO technology, apply the level of megasonic energy needed to remove random defects without incurring the pattern damage created by transient cavitation in conventional megasonic cleaning.

We have demonstrated the damage-free or low-damage cleaning capabilities of TEBO technology on customers’ patterned wafers as small as 1xnm (16nm to 19nm), and we believe TEBO technology will be applicable in even smaller fabrication process nodes.

TEBO technology can be applied in manufacturing processes for conventional 2D chips with fine features and advanced chips with 3D structures, including Fin Field Effect Transistors or FinFET, DRAM, 3D NAND and 3D cross point memory, and we expect it will be applicable to other 3D architectures developed in the future, such as carbon nanotubes and quantum devices.

As a result of the thorough, controlled nature of TEBO processes, cleaning time for TEBO-based solutions may take longer than conventional megasonic cleaning processes.

Conventional processes have proven ineffective, however, for process nodes of 20nm or less, and we believe the increased yield that can be achieved by

using TEBO technology for nodes up to 70nm can more than offset the cost of the additional time in utilizing TEBO technology.

TEBO Applications

At process nodes of 28nm and less, chip makers face escalating challenges in eliminating nanometric particles and maintaining the condition of inside pattern surfaces.

In order to maintain chip

quality and avoid yield loss, cleaning technologies must control random defects of diminishing killer defect sizes, without roughing or otherwise damaging surfaces of transistors, interconnects or other wafer features.

TEBO technology can be

applied in numerous steps throughout the manufacturing process flow for effective, damage-free cleaning:

In order to maintain chip quality and avoid yield loss, cleaning technologies must control random defects of diminishing killer defect sizes, without roughing or otherwise damaging surfaces of transistors, interconnects or other wafer features.

TEBO technology can be applied in numerous steps throughout the manufacturing process flow for effective, damage-free cleaning:

• Memory Chips:

We estimate that TEBO technology can be applied in as many as 50 steps in the fabrication of a DRAM chip, consisting of up to 10 steps in cleaning ISO

structures, 20 steps in cleaning buried gates, and 20 steps in cleaning high aspect-ratio storage nodes and stacked films.

We estimate that TEBO technology can be applied in as many as 50 steps in the fabrication of a DRAM chip, consisting of up to 10 steps in cleaning ISO structures, 20 steps in cleaning buried gates, and 20 steps in cleaning high aspect-ratio storage nodes and stacked films.

• Logic Chips:

In the fabrication process for a logic chip with a FinFET structure, we estimate that TEBO technology can be used in 15 or more cleaning steps.

For purposes of solving inside pattern surface conditions for memory or logic chips, TEBO technology uses environmentally friendly dilute chemicals such as RCA SC-1 and hydrogen gas doped

functional water.

For purposes of solving inside pattern surface conditions for memory or logic chips, TEBO technology uses environmentally friendly dilute chemicals such as RCA SC-1 and hydrogen gas doped functional water.

TEBO Equipment

We offer two models of wet wafer cleaning equipment based on our TEBO technology, Ultra C TEBO II and Ultra C TEBO V.

Each of these models is a single-wafer, serial-processing tool that can be

configured to customer specifications and, in conjunction with appropriate dilute chemicals, used at numerous manufacturing processing steps for effective, damage-free cleaning of chips at process nodes of 28nm or less.

TEBO equipment solves

the problem of pattern damage caused by transient cavitation in conventional jet spray and megasonic cleaning processes, providing better particle removal efficiency with limited material loss or roughing.

TEBO equipment is being evaluated by a

select group of leading memory and logic chip customers.

Each of these models is a single-wafer, serial-processing tool that can be configured to customer specifications and, in conjunction with appropriate dilute chemicals, used at numerous manufacturing processing steps for effective, damage-free cleaning of chips at process nodes of 28nm or less.

TEBO equipment solves the problem of pattern damage caused by transient cavitation in conventional jet spray and megasonic cleaning processes, providing better particle

removal efficiency with limited material loss or roughing.

TEBO equipment is being evaluated by a select group of leading memory and logic chip customers.

Each model of TEBO equipment includes:

14 unchanged sentences

• EFEM module consisting of 4 load ports, 1 transfer robot and 1 process robot:

● chemical delivery module for delivery of isopropyl alcohol, dilute hydrofluoric acid, RCA SC-1 solution, functional de-ionized water and carbon

dioxide to each of the chambers.

• chemical delivery module for delivery of isopropyl alcohol, dilute hydrofluoric acid, RCA SC-1 solution, functional de-ionized water and carbon dioxide to each of the chambers.

Tahoe Overview

Our Ultra-C Tahoe wafer cleaning tool can deliver high cleaning performance using significantly less sulfuric acid and hydrogen peroxide than is typically consumed by conventional high-temperature

single-wafer cleaning tools.

During normal single-wafer cleaning processes, only a fraction of the acid reacts with the wafer surface, while the majority is wasted as acid spins off the wafer and requires significant cost and effort to be

Our Ultra-C Tahoe wafer cleaning tool can deliver high cleaning performance using significantly less sulfuric acid and hydrogen peroxide than is typically consumed by conventional high-temperature single-wafer cleaning tools.

Tahoe employs a proprietary hybrid approach in which the sulfuric acid cleaning steps are processed in batch mode, and the final stage cleaning are processed with single-wafer cleaning technologies.

In addition to providing cost

savings resulting from vastly reduced sulfuric acid consumption, Ultra-C Tahoe meets the needs of customers who face increased environmental regulations and demand new, more environmentally friendly tools.

We delivered our first Ultra C Tahoe

tool to a strategic customer in 2019.

In addition to providing cost savings resulting from vastly reduced sulfuric acid consumption, Ultra-C Tahoe meets the needs of customers who face increased environmental regulations and demand new, more environmentally friendly tools.

We delivered our first Ultra C Tahoe tool to a strategic customer in 2019.

Advanced Packaging and other Back-End Processing Tools

We leverage our technology and expertise to provide a range of single-wafer tools for back-end wafer assembly and packaging factories.

We develop, manufacture and sell a wide range of advanced

packaging tools, such as coaters, developers, photoresist strippers, scrubbers, wet etchers and copper-plating tools.

We focus on providing custom-made, differentiated equipment that incorporates customer-requested features at a competitive

We develop, manufacture and sell a wide range of advanced packaging tools, such as coaters, developers, photoresist strippers, scrubbers, wet etchers and copper-plating tools.

We focus on providing custom-made, differentiated equipment that incorporates customer-requested features at a competitive price.

For example, our Ultra C Coater is used in applying photoresist, a light-sensitive material used in photolithography to transfer a pattern from a mask onto a wafer.

Coaters typically provide input

and output elevators, shuttle systems and other devices to handle and transport wafers during the coating process.

Coaters typically provide input and output elevators, shuttle systems and other devices to handle and transport wafers during the coating process.

Unlike most coaters, the Ultra C Coater is fully automated.

Based on requests from customers, we developed and incorporated the

special function of chamber auto-clean module into the Ultra C Coater, which further differentiates it from other products in the market by reducing or eliminating the cleaning of shroud in the coater which increases the tool’s continuous

production time.

Based on requests from customers, we developed and incorporated the special function of chamber auto-clean module into the Ultra C Coater, which further differentiates it from other products in the market by reducing or eliminating the cleaning of shroud in the coater which increases the tool’s continuous production time.

The Ultra C Coater is designed to deliver improved throughput and more efficient tool utilization while eliminating particle generation.

1 unchanged sentence

Ultra ECP ap, which delivers a uniform metal layer to finished wafers prior to packaging;

Ultra C Developer, which applies liquid developer to selected

parts of photoresist to resolve an image;

Ultra C Developer, which applies liquid developer to selected parts of photoresist to resolve an image;

Ultra C PR Megasonic-Assisted Stripper, which removes photoresist;

Ultra C Scrubber, which scrubs and cleans wafers;

Ultra C Thin Wafer Scrubber, which addresses a sub-market of cleaning very thin

wafers for certain Asian assembly factories;

Ultra C Thin Wafer Scrubber, which addresses a sub-market of cleaning very thin wafers for certain Asian assembly factories;

and Ultra C Wet Etcher, which etches silicon wafers and copper and titanium interconnects.

Our Customers

Since 2009 we have delivered more than 380 wet cleaning and other front-end processing tools, more than 290 of which were repeat orders or acceptances upon contractual performance obligations

having been met and thereby generated revenue to us.

The balance of the delivered tools is awaiting customer acceptance should contractual conditions be met.

To date, substantially all of our sales of equipment for semiconductor-manufacturing

have been to customers located in Asia, and we anticipate that a substantial majority of our revenue from these products will continue to come from customers located in this region for the foreseeable future.

We have begun to add to our efforts

to further address customers in North America, Western Europe and Southeast Asia, by expanding our direct sales teams and increasing our global marketing activities.

We generate most of our revenue from a limited number of customers as the result of our strategy of initially placing equipment with a small number of leading chip manufacturers that are driving

technology trends and key capability implementation.

Since 2009 we have delivered more than 765 tools to our customers , more than 650 of which were repeat orders or acceptances upon contractual performance obligations having been met and thereby generated revenue to us.

The balance of the delivered tools is subject to the customer's acceptance of the tool upon the tool's satisfaction of applicable contractual requirements or subject to the customer's subsequent discretionary commitment to purchase the tool.

To date, substantially all of our sales of equipment for semiconductor-manufacturing have been to customers located in Asia, and we anticipate that a substantial majority of our revenue from these products will continue to come from customers located in this region for the foreseeable future.

We have begun to add to our efforts to further address customers in North America, Western Europe and Southeast Asia, by expanding our direct sales teams and increasing our global marketing activities.

Our front-end customers have included:

Shanghai Huali Microelectronics Corporation, together with Huahong Semiconductor Ltd., collectively known as The Shanghai Huahong (Group) Company, Ltd., or The Huali Huahong Group, a leading mainland China-based foundry;

Semiconductor Manufacturing International Corporation, or SMIC, a leading mainland China-based foundry;

SK Hynix Inc., a leading Korean memory chip company;

Yangtze Memory Technologies Co., Ltd., or YMTC, a leading mainland China-based memory chip company, together with one of its subsidiaries;

ChangXin Memory Technologies, or CXMT, a leading mainland China-based memory chip company;

and SiEn, a leading mainland China-based power-semiconductor chip company.

Our wafer assembly and packaging customers have included:

Jiangyin Changdian Advanced Packaging Co.

Ltd., a mainland China-based wafer bumping packaging house that is a subsidiary of JCET Group Co., Ltd.;

Nantong Tongfu Microelectronics Co., Ltd., a mainland China-based chip assembly and testing company that is a subsidiary of Nantong Fujitsu Microelectronics Co., Ltd.;

Nepes Co., Ltd., a semiconductor packaging company based in Korea;

and Wafer Works Corporation, a mainland China-based wafer supplier.

In 2023, 45.5% of our revenue was derived from three customers:

The Huali Huahong Group, a leading PRC-based foundry, accounted for 18.2% of our revenue;

SMIC, a leading PRC-based foundry,

accounted for 15.6% of our revenue, and YMTC, a leading PRC-based memory chip company, together with one of its subsidiaries, accounted for 10.0% of our revenue.

In 2021, 48.9% of our revenue was derived from two customers:

The Huali Huahong

Group accounted for 28.1% of our revenue;

and YMTC, together with one of its subsidiaries, accounted for 20.8% of our revenue.

SMIC accounted for 16.7% of our revenue;

SiEn accounted for 15.4% of our revenue;

accounted for 13.4% of our revenue.

In 2022, 43.8% of our revenue was derived from three customers:

The Huali Huahong Group accounted for 36.9% of our

YMTC, together with one of its subsidiaries, accounted for 26.8% of our revenue;

and SMIC accounted for 12.1% of our revenue.

For our back-end wafer assembly and packaging customers, we focus on providing custom-made, differentiated equipment that incorporates a customer’s requested features at a competitive cost of

Our customers for advanced packaging, wafer processing, and other back-end processing tools have included Jiangyin Changdian Advanced Packaging Co.

Ltd., a leading PRC-based wafer bumping packaging house that is a subsidiary of JCET

Group Co., Ltd.;

Nantong Tongfu Microelectronics Co., Ltd., a PRC-based chip assembly and testing company that is a subsidiary of Nantong Fujitsu Microelectronics Co., Ltd.;

Nepes Co., Ltd., a semiconductor packaging company based in South

Korea which acquired the operations of Deca Technologies’ Philippines manufacturing facility in 2020;

and Wafer Works Corporation, a leading PRC-based wafer supplier.

The Huali Huahong Group;

accounted for 18.2% of our revenue;

SMIC accounted for 15.6% of our revenue, and YMTC accounted for 10.0% of our revenue.

In 2021, 48.9% of our revenue was derived from two customers:

The Huali Huahong Group accounted for 28.1% of our revenue;

and YMTC accounted for 20.8% of our revenue.

Sales and Marketing

We market and sell our products worldwide using a combination of our direct sales force and third-party representatives.

We employ direct sales teams in Asia, Europe and North America, and have

located these teams near our customers, primarily in the PRC, South Korea, Taiwan and the United States.

Each salesperson has specific local market expertise.

We also employ field application engineers, who are typically co-located with our

direct sales teams, to provide technical pre- and post-sale support tours and other assistance to existing and potential customers throughout the customers’ fab planning and production line qualification and fab expansion phases.

application engineers are organized by end markets as well as core competencies in hardware, control system, software and process development to support our customers.

To supplement our direct sales teams, we have contacts with several independent sales representatives in the PRC, South Korea and Taiwan.

We select these independent representatives based on their

ability to provide effective field sales, marketing forecast and technical requirement updates for our products.

We employ direct sales teams in mainland China, the United States, Southeast Asia, and Europe.

We also employ field application engineers, who are typically co-located with our direct sales teams, to provide technical pre- and post-sale support and other assistance to existing and potential customers throughout the customers’ fab planning and production line qualification and fab expansion phases.

Our field application engineers are organized by end markets as well as core competencies in hardware, control system, software and process development to support our customers.

To supplement our direct sales teams, we have contacts with several independent sales representatives in mainland China, Korea and Taiwan.

We select these independent representatives based on their ability to provide effective field sales, marketing forecast and technical requirement updates for our products.

In the case of representatives, our customers place purchase orders with us directly rather than with the representatives.

Our sales have historically been made using purchase orders with agreed technical specifications.

Our sales terms and conditions are generally consistent with industry practice but may vary from

customer to customer.

Our sales terms and conditions are generally consistent with industry practice but may vary from customer to customer.

We seek to obtain a purchase order two to six months ahead of the customer’s desired delivery date.

Consistent with industry practice, we allow customers to reschedule or cancel orders at a certain cost to them on

relatively short notice.

Consistent with industry practice, we allow customers to reschedule or cancel orders at a certain cost to them on relatively short notice.

Because of our relatively short delivery period and our practice of permitting rescheduling or cancellation, we believe that backlog is not a reliable indicator of our future revenue.

Our marketing team focuses on our product strategy and technology road maps, product marketing, new product introduction processes, demand assessment and competitive analysis, customer requirement

communication and public relations.

Our marketing team focuses on our product strategy and technology road maps, product marketing, new product introduction processes, demand assessment and competitive analysis, customer requirement communication and public relations.

Our marketing team also has the responsibility to conduct environmental scans, study industry trends and arrange our participation at major trade shows.

Manufacturing

We conduct a substantial majority of our product development, manufacturing, support and services in the PRC, with additional product development and subsystem production in South Korea.

Substantially all of our tools are built to order at our manufacturing facilities in the Pudong region of Shanghai, which now encompass a total of 236,000 square feet of floor space for production capacity.

We conduct a substantial majority of our product development, manufacturing, support and services in mainland China, with additional product development and subsystem production in Korea.

Substantially all of our tools are built to order at our manufacturing facilities in the Pudong region of Shanghai, which now encomp ass a total of 236,000 square f eet of floor space for production capacity.

In May 2020 ACM Shanghai, through its wholly owned subsidiary ACM Shengwei, entered into an agreement for a land use right in the Lingang region of Shanghai.

In July 2020 ACM Shengwei began a

multi-year construction project for a new development and production center.

The planned 1,000,000 square foot facility will incorporate state-of-the-art manufacturing systems and automation technologies and will provide the floor space to

support significantly more production capacity and related research and development activities when fully staffed and supplied.

In July 2020 ACM Shengwei began a multi-year construction project for a new development and production center.

The planned 1,000,000 square foot facility will incorporate state-of-the-art manufacturing systems and automation technologies and will provide the floor space to support significantly more production capacity and related research and development activities when fully staffed and supplied.

Properties,” of Part I of this report.

Our experience has shown that chip manufacturers in the PRC and throughout Asia demand equipment meeting their specific technical requirements and prefer building relationships with local

requirements, encourage them to adopt our SAPS, TEBO, Tahoe, ECP, furnace and other technologies in our current portfolio, and enable us to design innovative products and solutions to address their needs.

Currently substantially all of our staff are able to work at both of our Shanghai facilities, and to date we have not experienced absenteeism of management or other key employees, other than

certain of our executive officers being delayed in traveling between the PRC, our California office, and other global locations, and a significant number of ACM Shanghai employees missing work in late 2022 and early 2023 for one or several

weeks due to COVID-19 related illness following relaxation of the PRC’s zero-COVID policies in December 2022.

For additional information, see “Item 7.

Management’s Discussion and Analysis of Financial Condition and Results of

Operations—COVID-19 Pandemic,” of Part II of this report.

Our experience has shown that chip manufacturers in mainland China and throughout Asia demand equipment meeting their specific technical requirements and prefer building relationships with local suppliers.

We will continue to seek to leverage our local presence to address the growing market for semiconductor manufacturing equipment in the region by working closely with regional chip manufacturers to understand their specific requirements, encourage them to adopt our SAPS, TEBO, Tahoe, ECP, furnace, Track, PECVD, and other technologies in our current portfolio, and enable us to design innovative products and solutions to address their needs.

We purchase some of the components and assemblies that we include in our products from single source suppliers.

We believe that we could obtain and qualify alternative sources to supply these

We believe that we could obtain and qualify alternative sources to supply these components.

Nevertheless, any prolonged inability to obtain these components could have an adverse effect on our operating results and could unfavorably impact our customer relationships.

Please see “Item 1A.

Risk Factors—Risks Related to Our

Business and Our Industry—We depend on a limited number of suppliers, including single source suppliers, for critical components and assemblies, and our business could be disrupted if they are unable to meet our needs.”

Risk Factors—Risks Related to Our Business and Our Industry—We depend on a limited number of suppliers, including single source suppliers, for critical components and assemblies, and our business could be disrupted if they are unable to meet our needs.”

Research and Development

1 unchanged sentence

For this reason, we devote significant financial and personnel resources to research and development.

Our research and development team is comprised of highly skilled engineers and technologists with extensive experience in megasonic

technology, cleaning processes and chemistry, mechanical design, and control system design.

For the foreseeable future we are focusing on enhancing our Ultra C SAPS, TEBO, Tahoe, ECP, furnace and other tools and integrating additional capabilities to meet and anticipate requirements

from our existing and potential customers.

Our research and development team is comprised of highly skilled engineers and technologists with extensive experience in megasonic technology, cleaning processes and chemistry, mechanical design, and control system design.

For the foreseeable future we are focusing on enhancing our Ultra C SAPS, TEBO, Tahoe, ECP, furnace and other tools and integrating additional capabilities to meet and anticipate requirements from our existing and potential customers.

Our particular areas of focus include development of the following:

7 unchanged sentences

Longer term, we are working on new proprietary process capabilities based on our existing tool hardware platforms.

We are also working to integrate our tools with third-party tools in adjacent

process areas in the chip manufacturing flow.

We are also working to integrate our tools with third-party tools in adjacent process areas in the chip manufacturing flow.

Our research and development expense totaled $92.7 million or 16.6% of revenue in 2023, $62.2 million or 16.0% of revenue in 2022, and $34.2 million or 13.2% of revenue in 2021.

continue to invest in research and development to support and enhance our existing cleaning products and to develop future product offerings to build and maintain our technology leadership position.

We intend to continue to invest in research and development to support and enhance our existing cleaning products and to develop future product offerings to build and maintain our technology leadership position.

Intellectual Property

Our success and future revenue growth depend, in part, on our ability to protect our intellectual property.

We control access to and use of our proprietary technologies, software and other

confidential information through the use of internal and external controls, including contractual protections with employees, consultants, advisors, customers, partners and suppliers.

We rely primarily on patent, copyright, trademark and trade

secret laws, as well as confidentiality procedures, to protect our proprietary technologies and processes.

All employees and consultants are required to execute confidentiality agreements in connection with their employment and consulting

relationships with us.

We control access to and use of our proprietary technologies, software and other confidential information through the use of internal and external controls, including contractual protections with employees, consultants, advisors, customers, partners and suppliers.

We rely primarily on patent, copyright, trademark and trade secret laws, as well as confidentiality procedures, to protect our proprietary technologies and processes.

All employees and consultants are required to execute confidentiality agreements in connection with their employment and consulting relationships with us.

We also require them to agree to disclose and assign to us all inventions conceived or made in connection with the employment or consulting relationship.

We have aggressively pursued intellectual property since our founding in 1998.

We focus our patent filing efforts in the United States, and, when justified by cost and strategic importance, we

file corresponding foreign patent applications in strategic jurisdictions such as the European Union, the PRC, Japan, Singapore, South Korea, and Taiwan.

Our patent strategy is designed to provide a balance between the need for coverage in our

strategic markets and the need to maintain costs at a reasonable level.

We focus our patent filing efforts in the United States, and, when justified by cost and strategic importance, we file corresponding foreign patent applications in strategic jurisdictions such as the European Union, mainland China, Japan, Singapore, Korea, and Taiwan.

Our patent strategy is designed to provide a balance between the need for coverage in our strategic markets and the need to maintain costs at a reasonable level.

As of December 31, 2023, we had 64 issued patents, and 29 patents pending, in the United States.

These patents carry expiration dates from 2027 through 2038.

Many of the US patents and

applications have also been filed internationally, in one or more of the European Union, Japan, PRC, Singapore, South Korea, and Taiwan.

Specifically, we own patents in wafer cleaning, electro-polishing and plating, wafer preparation, and other

semiconductor processing technologies.

We have been issued more than 448 patents in the United States, the PRC, Japan, Korea, Singapore and Taiwan.

Many of the US patents and applications have also been filed internationally, including one or more of the European Union, Japan, mainland China, Singapore, Korea, and Taiwan.

Specifically, we own patents in wafer cleaning, electro-polishing and plating, wafer preparation, and other semiconductor processing technologies.

We have been issued more than 498 patents in the United States, mainland China, Japan, Korea, Singapore and Taiwan.

We manufacture advanced single-wafer cleaning systems equipped with our SAPS, TEBO and Tahoe technologies.

Our wafer cleaning technologies are protected by US Patent Numbers 8580042, 8671961,

9070723, 9281177, 9492852, 9595457, 9633833, 10020208, 10910244, 11103898, 11037804, 11141762, 11462423, 11257667, and 11298727, as well as their corresponding international patents.

We have 48 patents granted internationally protecting our

SAPS technologies.

We also have filed 11 international patent applications for key TEBO technologies, and 4 for Tahoe, in accordance with the Patent Cooperation Treaty, in anticipation of filing in the U.S.

national phase.

In addition to the above core technologies, we have technologies for SFP and ECP that are used in certain of our tools.

SFP is an integral part of the electro polishing process.

Our technology was

a breakthrough in electro-chemical-copper-planarization technology when it was first introduced, because it can polish, stress-free, copper layers used in copper low-K interconnects.

Our innovations in SFP and ECP are reflected in US Patent

Numbers 6638863, 8518224, 10227705, and 11008669, and their corresponding international counterparts.

We also have technologies in other semiconductor processing areas, such as wafer preparation and some specific processing steps.

The wafer preparation technology is covered by US Patent Numbers

8383429 and 9295167.

The specific processing steps include US Patent Number 8598039 titled “Barrier layer removal method and apparatus,” and US Patent Number 10615073 titled “method for removing barrier layer for minimizing sidewall recess.”

We have 57 patents granted internationally protecting our SAPS technologies, and we have filed 11 international patent applications for key TEBO technologies, and 5 for Tahoe, in accordance with the Patent Cooperation Treaty.

In addition we have patented technologies for SFP and ECP that are embedded in certain tools.

We also have patented technologies in other semiconductor processing areas, including wafer preparation and several specific processing steps.

To date we have not granted licenses to third parties under the patents described above.

Not all of these patents have been implemented in products.

We may enter into licensing or cross-licensing

arrangements with other companies in the future.

We may enter into licensing or cross-licensing arrangements with other companies in the future.

We cannot assure you that any patents will issue from any of our pending applications.

Any rights granted under any of our existing or future patents may not provide meaningful protection or any

commercial advantage to us.

With respect to our other proprietary rights, it may be possible for third parties to copy or otherwise obtain and use our proprietary technology or marks without authorization or to develop similar technology

independently.

The semiconductor equipment industry is characterized by vigorous protection and pursuit of intellectual property rights or positions, which have resulted in often protracted and expensive

Any rights granted under any of our existing or future patents may not provide meaningful protection or any commercial advantage to us.

The semiconductor equipment industry is characterized by vigorous protection and pursuit of intellectual property rights or positions, which have resulted in often protracted and expensive litigation.

We may in the future initiate claims or litigation against third parties to determine the validity and scope of proprietary rights of others.

In addition, we may in the future initiate litigation to enforce our intellectual property

rights or the rights of our customers or to protect our trade secrets.

In addition, we may in the future initiate litigation to enforce our intellectual property rights or the rights of our customers or to protect our trade secrets.

Our customers could become the target of litigation relating to the patent or other intellectual property rights of others.

This could trigger technical support and indemnification obligations in

some of our customer agreements.

This could trigger technical support and indemnification obligations in some of our customer agreements.

These obligations could result in substantial expenses, including the payment by us of costs and damages related to claims of patent infringement.

In addition to the time and expense required for us to provide

support or indemnification to our customers, any such litigation could disrupt the businesses of our customers, which in turn could hurt our relations with our customers and cause the sale of our products to decrease.

We do not have any

insurance coverage for intellectual property infringement claims for which we may be obligated to provide indemnification.

In addition to the time and expense required for us to provide support or indemnification to our customers, any such litigation could disrupt the businesses of our customers, which in turn could hurt our relations with our customers and cause the sale of our products to decrease.

We do not have any insurance coverage for intellectual property infringement claims for which we may be obligated to provide indemnification.

Additional information about the risks relating to our intellectual property is provided under “Item 1A.

1 unchanged sentence

The chip equipment industry is characterized by rapid change and is highly competitive throughout the world.

We compete with semiconductor equipment companies located around the world, and we may

also face competition from new and emerging companies, including new competitors from the PRC.

We consider our principal competitors to be those companies that provide wafer cleaning and electrical plating products to the market, including Lam

Research Corporation, NAURA Technology Group Co., Ltd., Mujin Electronics Co., Ltd., SCREEN SPE USA, LLC (a subsidiary of SCREEN Holdings Co., Ltd.), SEMES Co.

We compete with semiconductor equipment companies located around the world, and we may also face competition from new and emerging companies, including new competitors from mainland China.

We consider our principal competitors to be those companies that provide wafer cleaning and electrical plating products to the market, including Lam Research Corporation, NAURA Technology Group Co., Ltd., Mujin Electronics Co., Ltd., SCREEN SPE USA, LLC (a subsidiary of SCREEN Holdings Co., Ltd.), SEMES Co.

Ltd., Tokyo Electron Ltd.

and Kokusai Semiconductor Equipment Corporation.

competitors for our newly-introduced PECVD and Track products include Lam Research Corporation, Applied Materials, Inc., KINGSEMI Co., Ltd.

and Suzho Jingtuo Semiconductor Technology Co., Ltd.

Key competitors for our newly-introduced PECVD and Track products include Lam Research Corporation, Applied Materials, Inc., KINGSEMI Co., Ltd.

and Suzhou Jingtuo Semiconductor Technology Co., Ltd.

Compared to our company, our current and potential competitors may have:

• better established credibility and market reputations, longer operating histories, and broader product offerings;

significantly greater financial, technical, marketing and other resources, which may allow them to pursue design, development, manufacturing, sales, marketing, distribution and service support of their

• significantly greater financial, technical, marketing and other resources, which may allow them to pursue design, development, manufacturing, sales, marketing, distribution and service support of their products;

• more extensive customer and partner relationships, which may position them to identify and respond more successfully to market developments and changes in customer demands;

1 unchanged sentence

The principal competitive factors in our market include:

performance of products, including particle removal efficiency, rate of damage to wafer structures, high temperature chemistry, throughput, tool uptime and reliability, safety, chemical waste treatment, and

environmental impact;

• performance of products, including particle removal efficiency, rate of damage to wafer structures, high temperature chemistry, throughput, tool uptime and reliability, safety, chemical waste treatment, and environmental impact;

• gap filling capability, the deposited film thickness uniformity within wafer and wafer to wafer, particle generated on the wafer during the processes;

6 unchanged sentences

In addition, semiconductor manufacturers must make a substantial investment to qualify and integrate new equipment into semiconductor production lines.

Some manufacturers began fabricating chips

for the 5nm node in 2020 and the 3nm node in 2022.

Once a semiconductor manufacturer has selected a particular supplier’s equipment and qualified it for production, the manufacturer generally maintains that selection for that specific

production application and technology node as long as the supplier’s products demonstrate performance to specification in the installed base.

Accordingly, we may experience difficulty in selling to a given manufacturer if that manufacturer has

qualified a competitor’s equipment.

Some manufacturers began fabricating chips for the 5nm node in 2020 and the 3nm node in 2022.

Once a semiconductor manufacturer has selected a particular supplier’s equipment and qualified it for production, the manufacturer generally maintains that selection for that specific production application and technology node as long as the supplier’s products demonstrate performance to specification in the installed base.

Accordingly, we may experience difficulty in selling to a given manufacturer if that manufacturer has qualified a competitor’s equipment.

If, however, that cleaning equipment constrains chip yield, we expect, based on our experience to date, that the manufacturer will evaluate implementing new equipment that cleans more effectively.

We intend to address the high-end fabrication market with advanced nodes, and we believe we compete favorably with respect to the factors described above.

Most of our competitors offer

single-wafer cleaning products using jet spray technology, which has relatively poor particle removal efficiency for random defects less than 30nm in size and presents increased risk of damage to the fragile patterned architectures of wafers at

advanced process nodes.

Certain of our competitors offer single-wafer cleaning products with megasonic cleaning capability, but we believe these products, which use conventional megasonic technology, are unable to maintain energy dose

uniformity on the entire wafer and often lack the ability to repeat the requisite uniform energy dose wafer to wafer in production, resulting in poor efficiency in removing random defects, longer processing time and greater loss of material.

addition, these conventional megasonic products generate transient cavitation, which results in more incidents of damage to wafer structures with feature sizes of 70nm or less.

We design our cleaning tools equipped with our proprietary SAPS,

TEBO and Tahoe technologies, which we believe offer better performance, much less chemical consumption, and lower cost of consumables, including at advanced process nodes of 22nm or less.

Human Capital

As of December 31, 2022, we had 1,209 full-time equivalent employees, of whom 110 were in administration, 253 were in manufacturing, 519 were in research and development, and 327 were in sales and marketing and customer services.

Of these employees, 1,077 were located in mainland China and the Taiwan region, 119 were located in Korea and 13 were based in the United States.

never had a work stoppage, and none of our employees are represented by a labor organization or subject to any collective bargaining arrangements.

As of December 31, 2023, we ha d 1,590 fu ll-time equivalent employees, of whom 139 were in administration, 286 were in manufacturing, 733 were in research and development, and 432 were in sales and marketing and customer services.

Of these employees, 1,416 were located in mainland China and the Taiwan region, 159 were located in Korea and 15 were

based in the United States.

We have never had a work stoppage, and none of our employees are represented by a labor organization or subject to any collective bargaining arrangements.

We consider our employee relations to be good.

We compete in the highly competitive semiconductor equipment industry, with operations principally in the PRC.

Attracting, developing, and retaining skilled and experienced employees in research

and development, manufacturing, sales and marketing, and other positions is crucial to our ability to compete effectively.

Our ability to recruit and retain such employees depends on a number of factors, including our corporate culture and work

environment, informed by our values and behaviors, our corporate philosophy of talent development and career opportunities, and compensation and benefits.

Recruitment, Retention and Benefits

To attract and retain qualified employees and key talent, we offer total compensation packages that are competitive with comparable companies, particularly in the PRC and, specifically, Shanghai.

We compete in the highly competitive semiconductor equipment industry, with operations principally in mainland China.

Attracting, developing, and retaining skilled and experienced employees in research and development, manufacturing, sales and marketing, and other positions is crucial to our ability to compete effectively.

Our ability to recruit and retain such employees depends on a number of factors, including our corporate culture and work environment, informed by our values and behaviors, our corporate philosophy of talent development and career opportunities, and compensation and benefits.

To attract and retain qualified employees and key talent, we offer total compensation packages that are competitive with comparable companies, particularly in mainland China and, specifically, Shanghai.

We provide training and development programs to our employees, and we have trained many of our key engineers and managers for more than a decade.

Retention of these key employees is critical to

secure our future growth and technology development.

To assist in employee retention and recruitment, we offer employee housing in the Lingang region of Shanghai in connection with the completion of ACM Shanghai’s housing facility in Lingang,

where we are in the process of building a new research and development and production center.

Health and Safety, Pandemic Response

When it comes to employee safety, we are committed to providing a safe work environment for our employees that meets or exceeds local environmental, health, and safety laws and regulations.

result of the COVID-19 pandemic, we have augmented certain of our normal business practices to ensure that we promote health and safety for our employees.

We have established safety policies and protocols, and we regularly update our employees

with respect to any changes.

A majority of our workforce provide services that cannot be performed remotely, and we have prioritized the health of those individuals that continue to work at our facilities.

We have provided personal protective

equipment and cleaning supplies.

We require masks to be worn in our facilities and have prohibited all non-essential domestic and international travel for all employees.

We have also provided general information updates and support for our

employees to ensure that they have resources and information to protect their health and that of those around them, including their families and co-workers.

COVID-19 Pandemic

Following its initial outbreak in December 2019, COVID–19, or the coronavirus, spread across the PRC, the United States and globally.

The COVID–19 outbreak has affected our business and operating

results since the first quarter of 2020.

Since that time, travel between our offices in the United States and our facilities in the PRC has been and will likely continue to be restricted, which has and may continue to impact our ability to

effectively operate our company and to oversee our operations.

The COVID–19 situation continues to evolve, and it is impossible for us to predict the effect and ultimate impact of the COVID–19 outbreak on our business operations and results.

December 2022, the PRC government relaxed its zero-COVID policies, which resulted in large scale COVID-19 infections throughout China, including Shanghai.

A significant number of ACM Shanghai employees were also infected, and in many cases

missed work for one or several weeks, which caused administrative and operational challenges in late 2022 and early 2023.

We continue to monitor the impact of the COVID-19 pandemic on all aspects of our business, including our operations,

customers, suppliers and projects.

While the ongoing regulatory measures instituted or recommended in response to COVID–19 are expected to be temporary, the duration of the business disruptions, and related financial impact, of the outbreak

cannot be estimated at this time.

Management’s Discussion and Analysis of Financial Condition and Results of Operations—COVID‑19 Pandemic” of Part II of this report for additional discussion of our expectations and

estimates related to the COVID-19 Pandemic.

Retention of these key employees is critical to secure our future growth and technology development.

To assist in employee retention and recruitment, we offer employee housing in the Lingang region of Shanghai nearby our new research and development and production center.

Environmental

Severe weather events, including earthquakes, fires, floods, heat waves, hurricanes and other environmental disasters, could pose a threat to our manufacturing and research and development

activities through physical damage to our operating facilities or equipment or disruption of power supply or telecommunications infrastructure.

The frequency and intensity of severe weather events are reportedly increasing throughout the world

as part of broader climate changes.

Severe weather events, including earthquakes, fires, floods, heat waves, hurricanes and other environmental disasters, could pose a threat to our manufacturing and research and development activities through physical damage to our operating facilities or equipment or disruption of power supply or telecommunications infrastructure.

The frequency and intensity of severe weather events are reportedly increasing throughout the world as part of broader climate changes.

Global weather pattern changes may also pose long-term risks of physical impacts to our business.

We maintain disaster recovery and business continuity plans that would be implemented to help us recover in

the event of severe weather events that interrupt our business.

We maintain disaster recovery and business continuity plans that would be implemented to help us recover in the event of severe weather events that interrupt our business.

See “Item 1A.

1 unchanged sentence

Concerns about climate change have resulted in various laws and regulations that are intended to limit carbon emissions and address other environmental concerns.

In recent years, the PRC, where

our production facilities are located, has undertaken comprehensive sustainability initiatives that are requiring companies to meet new environmental standards and deal with higher energy and other production costs.

Environmental laws and

regulations may impose new or unexpected cost either directly through, for example, higher energy costs or indirectly through increased costs of compliance or of failing to comply with these laws and regulations.

These laws and regulations

might increase the cost of construction, maintenance and operation of our new research and development center and factory in the Lingang region of Shanghai.

In recent years, mainland China, where our production facilities are located, has undertaken comprehensive sustainability initiatives that are requiring companies to meet new environmental standards and deal with higher energy and other production costs.

Environmental laws and regulations may impose new or unexpected cost either directly through, for example, higher energy costs or indirectly through increased costs of compliance or of failing to comply with these laws and regulations.

These laws and regulations might increase the cost of construction, maintenance and operation of our new research and development center and factory in the Lingang region of Shanghai.

We do not currently expect that existing or pending climate change laws and regulations will be material to our results of operations in the foreseeable future.

Climate change could, however, have

a direct effect on our customer base of semiconductor fabricators, whose operations typically require copious quantities of power and water and a number of chemicals.

Chip fabrication operations often result in significant amounts of

wastewater, which can contain a number of harmful contaminants, including antimony, arsenic, hydrofluoric acid and hydrogen peroxide, that historically have resulted in groundwater pollution and related violations of environmental laws.

Climate change could, however, have a direct effect on our customer base of semiconductor fabricators, whose operations typically require copious quantities of power and water and a number of chemicals.

Chip fabrication operations often result in significant amounts of wastewater, which can contain a number of harmful contaminants, including antimony, arsenic, hydrofluoric acid and hydrogen peroxide, that historically have resulted in groundwater pollution and related violations of environmental laws.

Moreover, water and chemical demands for semiconductor fabrication are expected to increase with the production of more advanced chips at smaller process nodes.

As a result, some leading chip fabricators have begun to invest in conservation and

treatment technologies for water and chemicals.

As a result, some leading chip fabricators have begun to invest in conservation and treatment technologies for water and chemicals.

We have designed some of our tools to require significantly reduced levels of environmentally harmful chemicals, which helps customers face increased environmental laws and regulations.

TEBO technologies use environmentally friendly dilute chemicals, such as dilute hydrofluoric acid, RCA SC-1 solution, ozonated de-ionized water and functional de-ionized water with dissolved hydrogen.

In interconnect and barrier metals

applications based on SAPS technology, for example, these chemical solutions take the place of chemicals such as piranha solution, a high-temperature mixture of sulfuric acid and hydrogen peroxide used by conventional wet wafer cleaning

SAPS and TEBO technologies use environmentally friendly dilute chemicals, such as dilute hydrofluoric acid, RCA SC-1 solution, ozonated de-ionized water and functional de-ionized water with dissolved hydrogen.

In interconnect and barrier metals applications based on SAPS technology, for example, these chemical solutions take the place of chemicals such as piranha solution, a high-temperature mixture of sulfuric acid and hydrogen peroxide used by conventional wet wafer cleaning processes.

Similarly, Tahoe technology delivers high cleaning performance using significantly less sulfuric acid and hydrogen peroxide than is typically consumed by conventional high-temperature single-wafer cleaning tools.

For additional

information, see “—Our Technology and Product Offerings—Wet Cleaning Equipment for Front End Production Processes.”

For additional information, see “—Our Technology and Product Offerings—Wet Cleaning Equipment for Front End Production Processes.”

Available Information

1 unchanged sentence

Securities and Exchange Commission, or the SEC.

The SEC maintains a website at

www.sec.gov that contains reports, proxy and information statements, and other information regarding issuers that file electronically with the SEC.

Our Annual Reports on Form 10-K, Quarterly Reports on Form 10-Q, Current Reports on Form 8-K, proxy statements and amendments to those documents filed or furnished pursuant to Section 13(a) or

15(d) of the Securities Exchange Act of 1934, or the Exchange Act, are also available free of charge on our website at www.acmrcsh.com as soon as reasonably practicable after such reports are electronically filed with or furnished to the SEC.

Investors should note that we announce material information to our investors and others using filings with the SEC, press releases, public conference calls, webcasts or our website

(www.acmrcsh.com), including news and announcements regarding our financial performance, key personnel, our brands and our business strategy.

The SEC maintains a website at www.sec.gov that contains reports, proxy and information statements, and other information regarding issuers that file electronically with the SEC.

Our Annual Reports on Form 10-K, Quarterly Reports on Form 10-Q, Current Reports on Form 8-K, proxy statements and amendments to those documents filed or furnished pursuant to Section 13(a) or 15(d) of the Securities Exchange Act of 1934, or the Exchange Act, are also available free of charge on our website at www.acmrcsh.com as soon as reasonably practicable after such reports are electronically filed with or furnished to the SEC.

Investors should note that we announce material information to our investors and others using filings with the SEC, press releases, public conference calls, webcasts or our website (www.acmrcsh.com), including news and announcements regarding our financial performance, key personnel, our brands and our business strategy.

Information that we post on our corporate website could be deemed material to investors.

investors to review the information we post on these channels.

We may from time to time update the list of channels we will use to communicate information that could be deemed material and will post information about any such change on

www.acmrcsh.com.

We encourage investors to review the information we post on these channels.

We may from time to time update the list of channels we will use to communicate information that could be deemed material and will post information about any such change on www.acmrcsh.com.

The information on our website is not, and shall not be deemed to be, a part hereof or incorporated into this or any of our other filings with the SEC.

Compared sentence by sentence after normalising whitespace, quotation marks, case and digits, so re-formatting and restated figures do not read as changed language. Wording changes appear as one removal and one addition. The current filing and the prior one are authoritative.

What changed 10-K

Item 1. Business