The Inference-Compute Frontier and a Latency-Efficient Architecture for Limit Order Book Prediction — explained | StockTools Quant Research

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The Inference-Compute Frontier and a Latency-Efficient Architecture for Limit Order Book Prediction

C. Evans Hedges · 2026-06-24

what this means for investors // AI summary of the abstractNiche / specialist

The paper tests whether limit order book prediction shows a predictable trade-off between computation and accuracy, and finds that predictive loss versus compute follows a power law that extrapolates well (R²=0.941) to a held-out high-compute model family. It also shows this relationship is much weaker in latency terms, and introduces FastBiNLOB, a hardware-friendly architecture that matches or beats published accuracy benchmarks at lower latency.

Why it matters: For those building short-horizon order-book prediction systems, the work suggests that model accuracy scales predictably with compute, which could help budget resources, and that lower-latency architectures need not sacrifice predictive quality. This matters most for latency-sensitive execution or market-making research pipelines rather than typical investing.

Predictive loss versus compute in LOB models follows a power law that extrapolates across orders of magnitude.
Latency does not track compute cleanly, so faster models are not just scaled-down compute — architecture matters.
FastBiNLOB reportedly beats published macro-F1 targets at lower latency on the FI-2010 benchmark.

Applies to: limit order book prediction and low-latency execution/market-making model design

⚠ Results rest on a single academic benchmark (FI-2010) and measure predictive accuracy/latency, not live trading profitability.

ABSTRACT

We study whether a scaling-law-style inference-compute frontier appears in limit order book prediction. Using FI-2010 and a suite of models ranging from small decision trees to neural LOB architectures, we find that the realized empirical frontier of predictive loss versus structural forward work is well summarized by a power law. In particular, with MLPLOB held out as an architecture family, a power-law fit to the low- and mid-compute non-MLPLOB frontier extrapolates across multiple orders of magnitude and attains $R^2=0.941$ on the excluded high-compute MLPLOB target frontier. A similar exercise in latency space gives substantially weaker results, showing that latency is not merely noisy compute. We use this gap to motivate FastBiNLOB, a dense axis-separable LOB mixer built from hardware-friendly temporal and feature mixing operations. In a five-seed experiment, FastBiNLOB exceeds the published $y_{10}$ and $y_{100}$ macro-F1 targets at notably lower latency than existing published SOTA architectures.

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AI summary generated from the paper’s public abstract via arXiv; it may miss nuance — read the source before relying on it. Thank you to arXiv for its open-access interoperability; StockTools is not affiliated with arXiv, and all rights remain with the authors. Educational only, not financial advice.